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WINBOND I/O W83977F & W83977AF
W83977F/ AF Data Sheet Revision History
Pages Dates Versio n Versio n on Web 1 2 n.a. 2,3,6,8,9,10, 122,126,128132,134,138,168 3 4 5 6 7 8 9 117-125,127 9,10,120-122 127,135,136,169 VIII,IX,166-169 P118 53,54,58,61,62, 63,65,124,125 1,3,11,52,91,105, 109,110,111,113, 114,115,119,124, 130,131,148 03/10/97 0.58 Typo correction and data calibrated 01/30/97 02/13/97 03/03/97 05/24/97 7/15/97 11/17/97 0.52 0.53 0.54 0.55 0.56 0.57 Register Correction; pages rearranging. Spec. Correction; typo correction Spec. Correction; typo correction Add section 15.0; pages rearranging. CR24: Pin 22aPin1 Register Correction 01/20/97 01/27/97 0.50 0.51 First publication Spec. Correction; typo correction Main Contents
10
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
W83977F/ W83977AF
PRELIMINARY
TABLE OF CONTENTS
1. PIN DESCRIPTION........................................................................................................6
1.1 HOST INTERFACE....................................................................................................................................6 1.2 ADVANCED POWER MANAGEMENT....................................................................................................8 1.3 SERIAL PORT INTERFACE......................................................................................................................9 1.4 INFRARED INTERFACE.........................................................................................................................10 1.5 MULTI-MODE PARALLEL PORT ..........................................................................................................11 1.6 FDC INTERFACE ....................................................................................................................................16 1.7 KBC INTERFACE....................................................................................................................................17 1.8 RTC INTERFACE ....................................................................................................................................17 1.9 POWER PINS ...........................................................................................................................................17
2. FDC FUNCTIONAL DESCRIPTION...........................................................................18
2.1 W83977F/ AF FDC ...................................................................................................................................18 2.1.1 AT interface........................................................................................................................................18 2.1.2 FIFO (Data) .......................................................................................................................................18 2.1.3 Data Separator...................................................................................................................................19 2.1.4 Write Precompensation.......................................................................................................................19 2.1.5 Perpendicular Recording Mode ..........................................................................................................19 2.1.6 FDC Core...........................................................................................................................................20 2.1.7 FDC Commands .................................................................................................................................20 2.2 REGISTER DESCRIPTIONS....................................................................................................................31 2.2.1 Status Register A (SA Register) (Read base address + 0) ....................................................................31 2.2.2 Status Register B (SB Register) (Read base address + 1) ....................................................................33 2.2.3 Digital Output Register (DO Register) (Write base address + 2).........................................................35 2.2.4 Tape Drive Register (TD Register) (Read base address + 3) ...............................................................35 2.2.5 Main Status Register (MS Register) (Read base address + 4)..............................................................36 2.2.6 Data Rate Register (DR Register) (Write base address + 4)................................................................36 2.2.7 FIFO Register (R/W base address + 5) ...............................................................................................38 2.2.8 Digital Input Register (DI Register) (Read base address + 7) .............................................................40
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Publication Release Date:March 1998 Preliminary Revision 0.58
W83977F/ W83977AF
PRELIMINARY
2.2.9 Configuration Control Register (CC Register) (Write base address + 7) .............................................42
3. UART PORT ..................................................................................................................43
3.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B) ............................43 3.2 REGISTER ADDRESS .............................................................................................................................43 3.2.1 UART Control Register (UCR) (Read/Write).......................................................................................43 3.2.2 UART Status Register (USR) (Read/Write)..........................................................................................45 3.2.3 Handshake Control Register (HCR) (Read/Write) ...............................................................................46 3.2.4 Handshake Status Register (HSR) (Read/Write) ..................................................................................47 3.2.5 UART FIFO Control Register (UFR) (Write only)...............................................................................48 3.2.6 Interrupt Status Register (ISR) (Read only) .........................................................................................48 3.2.7 Interrupt Control Register (ICR) (Read/Write)....................................................................................49 3.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write)...................................................................50 3.2.9 User-defined Register (UDR) (Read/Write) .........................................................................................50
4. INFRARED (IR) PORT .................................................................................................52
4.1 IR REGISTER DESCRIPTION .................................................................................................................52 4.2 SET0-LEGACY/ADVANCED IR CONTROL AND STATUS REGISTERS.............................................53 4.2.1 Set0.Reg0 - Receiver/Transmitter Buffer Registers (RBR/TBR) (Read/Write) ......................................53 4.2.2 Set0.Reg1 - Interrupt Control Register (ICR)......................................................................................53 4.2.3 Set0.Reg2 - Interrupt Status Register/IR FIFO Control Register (ISR/UFR)........................................54 4.2.4 Set0.Reg3 - IR Control Register/Set Select Register (UCR/SSR): ........................................................57 4.2.5 Set0.Reg4 - Handshake Control Register (HCR) .................................................................................58 4.2.6 Set0.Reg5 - IR Status Register (USR)..................................................................................................59 4.2.7 Set0.Reg6 - Reserved..........................................................................................................................59 4.2.8 Set0.Reg7 - User Defined Register (UDR/AUDR) ...............................................................................59 4.3 SET1 - LEGACY BAUD RATE DIVISOR REGISTER ............................................................................60 4.3.1 Set1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) ...........................................................................61 4.3.2 Set1.Reg 2~7 ......................................................................................................................................61 4.4 SET2 - INTERRUPT STATUS OR IR FIFO CONTROL REGISTER (ISR/UFR)......................................61 4.4.1 Reg0, 1 - Advanced Baud Rate Divisor Latch (ABLL/ABHL) ..............................................................61 4.4.2 Reg2 - Advanced IR Control Register 1 (ADCR1)...............................................................................61 4.4.3 Reg3 - Sets Select Register (SSR)........................................................................................................62 4.4.4 Reg4 - Advanced IR Control Register 2 (ADCR2)...............................................................................62
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Publication Release Date:March 1998 Preliminary Revision 0.58
W83977F/ W83977AF
PRELIMINARY
4.4.5 Reg6 - Transmitter FIFO Depth (TXFDTH) (Read Only) ....................................................................64 4.4.6 Reg7 - Receiver FIFO Depth (RXFDTH) (Read Only).........................................................................64 4.5 SET3 - VERSION ID AND MAPPED CONTROL REGISTERS...............................................................64 4.5.1 Reg0 - Advanced IR ID (AUID) ..........................................................................................................64 4.5.2 Reg1 - Mapped IR Control Register (MP_UCR) .................................................................................64 4.5.3 Reg2 - Mapped IR FIFO Control Register (MP_UFR) ........................................................................65 4.5.4 Reg3 - Sets Select Register (SSR)........................................................................................................65 4.6 SET4 - TX/RX/TIMER COUNTER REGISTERS AND IR CONTROL REGISTERS. ..............................65 4.6.1 Set4.Reg0, 1 - Timer Value Register (TMRL/TMRH)...........................................................................65 4.6.2 Set4.Reg2 - Infrared Mode Select (IR_MSL) .......................................................................................65 4.6.3 Set4.Reg3 - Set Select Register (SSR)..................................................................................................66 4.6.4 Set4.Reg4, 5 - Transmitter Frame Length (TFRLL/TFRLH) ................................................................66 4.6.5 Set4.Reg6, 7 - Receiver Frame Length (RFRLL/RFRLH) ....................................................................66 4.7 SET 5 - FLOW CONTROL AND IR CONTROL AND FRAME STATUS FIFO REGISTERS .................67 4.7.1 Set5.Reg0, 1 - Flow Control Baud Rate Divisor Latch Register (FCDLL/ FCDHL).............................67 4.7.2 Set5.Reg2 - Flow Control Mode Operation (FC_MD) .........................................................................67 4.7.3 Set5.Reg3 - Sets Select Register (SSR) ................................................................................................68 4.7.4 Set5.Reg4 - Infrared Configure Register 1 (IRCFG1)..........................................................................68 4.7.5 Set5.Reg5 - Frame Status FIFO Register (FS_FO)..............................................................................68 4.7.6 Set5.Reg6, 7 - Receiver Frame Length FIFO (RFLFL/RFLFH) or Lost Frame Number (LST_NU) ......69 4.8 SET6 - IR PHYSICAL LAYER CONTROL REGISTERS.........................................................................69 4.8.1 Set6.Reg0 - Infrared Configure Register 2 (IR_CFG2)........................................................................70 4.8.2 Set6.Reg1 - MIR (1.152M/0.576M bps) Pulse Width ...........................................................................70 4.8.3 Set6.Reg2 - SIR Pulse Width...............................................................................................................71 4.8.4 Set6.Reg3 - Set Select Register ...........................................................................................................71 4.8.5 Set6.Reg4 - High Speed Infrared Beginning Flag Number (HIR_FNU) ..............................................71 4.9 SET7 - REMOTE CONTROL AND IR MODULE SELECTION REGISTERS .........................................72 4.9.1 Set7.Reg0 - Remote Infrared Receiver Control (RIR_RXC).................................................................72 4.9.2 Set7.Reg1 - Remote Infrared Transmitter Control (RIR_TXC).............................................................74 4.9.3 Set7.Reg2 - Remote Infrared Config Register (RIR_CFG)...................................................................74 4.9.4 Set7.Reg3 - Sets Select Register (SSR) ................................................................................................75 4.9.5 Set7.Reg4 - Infrared Module (Front End) Select 1 (IRM_SL1) ............................................................76 4.9.6 Set7.Reg5 - Infrared Module (Front End) Select 2 (IRM_SL2) ............................................................76
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Publication Release Date:March 1998 Preliminary Revision 0.58
W83977F/ W83977AF
PRELIMINARY
4.9.7 Set7.Reg6 - Infrared Module (Front End) Select 3 (IRM_SL3) ............................................................76 4.9.8 Set7.Reg7 - Infrared Module Control Register (IRM_CR)...................................................................77
5. PARALLEL PORT........................................................................................................78
5.1 PRINTER INTERFACE LOGIC ...............................................................................................................78 5.2 ENHANCED PARALLEL PORT (EPP)....................................................................................................79 5.2.1 Data Swapper .....................................................................................................................................79 5.2.2 Printer Status Buffer...........................................................................................................................80 5.2.3 Printer Control Latch and Printer Control Swapper ...........................................................................80 5.2.4 EPP Address Port...............................................................................................................................81 5.2.5 EPP Data Port 0-3 .............................................................................................................................82 5.2.6 Bit Map of Parallel Port and EPP Registers .......................................................................................82 5.2.7 EPP Pin Descriptions .........................................................................................................................83 5.2.8 EPP Operation ...................................................................................................................................83 5.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT .........................................................................84 5.3.1 ECP Register and Mode Definitions ...................................................................................................84 5.3.2 Data and ecpAFifo Port......................................................................................................................85 5.3.3 Device Status Register (DSR)..............................................................................................................85 5.3.4 Device Control Register (DCR) ..........................................................................................................86 5.3.5 cFifo (Parallel Port Data FIFO) Mode = 010.....................................................................................87 5.3.6 ecpDFifo (ECP Data FIFO) Mode = 011............................................................................................87 5.3.7 tFifo (Test FIFO Mode) Mode = 110 ..................................................................................................87 5.3.8 cnfgA (Configuration Register A) Mode = 111....................................................................................87 5.3.9 cnfgB (Configuration Register B) Mode = 111....................................................................................87 5.3.10 ecr (Extended Control Register) Mode = all .....................................................................................88 5.3.11 Bit Map of ECP Port Registers .........................................................................................................89 5.3.12 ECP Pin Descriptions.......................................................................................................................90 5.3.13 ECP Operation .................................................................................................................................91 5.3.14 FIFO Operation................................................................................................................................91 5.3.15 DMA Transfers .................................................................................................................................92 5.3.16 Programmed I/O (NON-DMA) Mode ................................................................................................92 5.4 EXTENSION FDD MODE (EXTFDD).....................................................................................................92 5.5 EXTENSION 2FDD MODE (EXT2FDD) .................................................................................................92
6. REAL-TIME CLOCK (RTC) AND "ON-NOW" CONTROL ....................................93
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Publication Release Date:March 1998 Preliminary Revision 0.58
W83977F/ W83977AF
PRELIMINARY
6.1 REGISTER ADDRESS MAP ....................................................................................................................93 6.2 UPDATE CYCLE .....................................................................................................................................95 6.3 REGISTERS .............................................................................................................................................96 6.3.1 Register 0Ah.......................................................................................................................................96 6.3.2 Register 0Bh (Read/Write) ..................................................................................................................98 6.3.3 Register 0Ch (Read only)....................................................................................................................99 6.3.4 Register D (Read only) .......................................................................................................................99 6.4 "ON-NOW" CONTROL..........................................................................................................................100 6.5 POWER-ON EVENTS............................................................................................................................100 6.6 POWER-OFF EVENTS ..........................................................................................................................100 6.7 REGISTERS ...........................................................................................................................................101 6.7.1 "ON-Now" Register 1 (Bank2 Register 49h).....................................................................................101 6.7.2 "On-Now" Register 2 (Bank2 Register 4Ah) ....................................................................................102 6.7.3 "On-Now" Register 3 (Bank2 Register 4Bh) ......................................................................................103 6.7.4 "On-Now" Register 4 (Bank2 Register 4Ch)......................................................................................104
7. KEYBOARD CONTROLLER ....................................................................................105
7.1 OUTPUT BUFFER..................................................................................................................................106 7.2 INPUT BUFFER .....................................................................................................................................106 7.3 STATUS REGISTER ..............................................................................................................................106 7.4 COMMANDS .........................................................................................................................................107 7.5 HARDWARE GATEA20/KEYBOARD RESET CONTROL LOGIC ......................................................109 7.5.1 KB Control Register (Logic Device 5, CR-F0) ..................................................................................109 7.5.2 Port 92 Control Register (Default Value = 0x24)..............................................................................109
8. GENERAL PURPOSE I/O...........................................................................................110
8.1 BASIC I/O FUNCTIONS ........................................................................................................................111 8.2 ALTERNATE I/O FUNCTIONS.............................................................................................................113 8.2.1 Interrupt Steering .............................................................................................................................113 8.2.2 Watch Dog Timer Output..................................................................................................................113 8.2.3 Power LED.......................................................................................................................................114 8.2.4 General Purpose Address Decoder ...................................................................................................114 8.2.5 General Purpose Write Strobe ..........................................................................................................114
9. PLUG AND PLAY CONFIGURATION .....................................................................114
9.1 COMPLY PNP........................................................................................................................................115
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Publication Release Date:March 1998 Preliminary Revision 0.58
W83977F/ W83977AF
PRELIMINARY
9.1.1 Wait for Key State ............................................................................................................................115 9.1.2 Sleep State........................................................................................................................................115 9.1.3 Isolation State ..................................................................................................................................115 9.1.4 Configure State.................................................................................................................................115 9.2 COMPATIBLE PNP ...............................................................................................................................116 9.2.1 Extended Function Registers ............................................................................................................116 9.2.2 Extended Functions Enable Registers (EFERs).................................................................................116 9.2.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs) .................116
10. CONFIGURATION REGISTER...............................................................................117
10.1 CHIP (GLOBAL) CONTROL REGISTER ............................................................................................117 10.2 LOGICAL DEVICE 0 (FDC) ................................................................................................................122 10.3 LOGICAL DEVICE 1 (PARALLEL PORT)..........................................................................................126 10.4 LOGICAL DEVICE 2 (UART A)) ......................................................................................................128 10.5 LOGICAL DEVICE 3 (UART B)..........................................................................................................129 10.6 LOGICAL DEVICE 4 (REAL TIME CLOCK)......................................................................................130 10.7 LOGICAL DEVICE 5 (KBC)................................................................................................................131 10.8 LOGICAL DEVICE 6 (IR)....................................................................................................................132 10.9 LOGICAL DEVICE 7 (AUXILIARY I/O PART I)................................................................................134 10.10 LOGICAL DEVICE 8 (AUXILIARY I/O PART II).............................................................................138
11. SPECIFICATIONS.....................................................................................................142
11.1 ABSOLUTE MAXIMUM RATINGS ....................................................................................................142 11.2 DC CHARACTERISTICS.....................................................................................................................142 11.3 AC CHARACTERISTICS.....................................................................................................................146 11.3.1 FDC: Data rate = 1 MB, 500 KB, 300 KB, 250 KB/sec. .................................................................146 11.3.2 UART/Parallel Port ........................................................................................................................148 11.3.3 Parallel Port Mode Parameters ......................................................................................................148 11.3.4 EPP Data or Address Read Cycle Timing Parameters ....................................................................149 11.3.5 EPP Data or Address Write Cycle Timing Parameters....................................................................150 11.3.6 Parallel Port FIFO Timing Parameters...........................................................................................151 11.3.7 ECP Parallel Port Forward Timing Parameters..............................................................................151 11.3.8 ECP Parallel Port Reverse Timing Parameters...............................................................................151 11.3.9 KBC Timing Parameters.................................................................................................................152
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Publication Release Date:March 1998 Preliminary Revision 0.58
W83977F/ W83977AF
PRELIMINARY
11.3.10 GPIO, ACPI, ROM Interface Timing Parameters..........................................................................153
12. TIMING WAVEFORMS ...........................................................................................154
12.1 FDC ......................................................................................................................................................154 12.2 UART/PARALLEL ...............................................................................................................................155 12.2.1 Modem Control Timing...................................................................................................................156 12.3 PARALLEL PORT................................................................................................................................157 12.3.1 Parallel Port Timing.......................................................................................................................157 12.3.2 EPP Data or Address Read Cycle (EPP Version 1.9) ......................................................................158 12.3.3 EPP Data or Address Write Cycle (EPP Version 1.9)......................................................................159 12.3.4 EPP Data or Address Read Cycle (EPP Version 1.7) ......................................................................160 12.3.5 EPP Data or Address Write Cycle (EPP Version 1.7)......................................................................161 12.3.6 Parallel Port FIFO Timing .............................................................................................................161 12.3.7 ECP Parallel Port Forward Timing ................................................................................................162 12.3.8 ECP Parallel Port Reverse Timing .................................................................................................162 12.4 KBC......................................................................................................................................................163 12.4.1 Write Cycle Timing.........................................................................................................................163 12.4.2 Read Cycle Timing .........................................................................................................................163 12.4.3 Send Data to K/B............................................................................................................................163 12.4.4 Receive Data from K/B ...................................................................................................................164 12.4.5 Input Clock.....................................................................................................................................164 12.4.6 Send Data to Mouse........................................................................................................................164 12.4.7 Receive Data from Mouse...............................................................................................................164 12.5 GPIO WRITE TIMING DIAGRAM ......................................................................................................165 12.6 MASTER RESET (MR) TIMING .........................................................................................................165 12.7 ACPI.....................................................................................................................................................165 12.7.1 PANSW Trigger and PSCTRL Timing.....................................................................................165 12.7.2 RIA , RIB , KLCK, MCLK, PWAKIN1, PWAKIN2 Trigger and PSCTRL Timing .....................166 12.7.3 PHRI Trigger and PSCTRL Timing..........................................................................................166
13. APPLICATION CIRCUITS.......................................................................................166
13.1 PARALLEL PORT EXTENSION FDD.................................................................................................166 13.2 PARALLEL PORT EXTENSION 2FDD...............................................................................................167 13.3 FOUR FDD MODE...............................................................................................................................167
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Publication Release Date:March 1998 Preliminary Revision 0.58
W83977F/ W83977AF
PRELIMINARY
14. ORDERING INFORMATION ..................................................................................168 15. HOW TO READ THE TOP MARKING ..................................................................168 16. PACKAGE DIMENSIONS ........................................................................................169
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Publication Release Date:March 1998 Preliminary Revision 0.58
W83977F/ W83977AF
PRELIMINARY GENERAL DESCRIPTION
This data sheet covers two products: W83977F, and W83977AF whose pin assignment, and most of the functions are the same. W83977AF is an advanced version of W83977F featuring the FIR function. W83977F/ AF is an evolving product from Winbond's most popular I/O chip W83877F --- which integrates the disk drive adapter, serial port (UART), IrDA 1.0 SIR, parallel port, configurable plugand-play registers in one chip --- plus additional powerful features: ACPI, 8042 keyboard controller with PS/2 mouse support, Real Time Clock, 14 general purpose I/O ports, full 16-bit address decoding, TV remote IR (Consumer IR, supporting NEC, RC-5, extended RC-5, and RECS-80 protocols). In addition, W83977AF provides the functions of IrDA 1.1 (MIR for 1.152M bps or FIR for 4M bps). The disk drive adapter functions of W83977F/ AF include a floppy disk drive controller compatible with the industry standard 82077/ 765, data separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt/ DMA logic. The wide range of functions integrated onto the W83977F/ AF greatly reduces the number of components required for interfacing with floppy disk drives. The W83977F/ AF supports up to four 360K, 720K, 1.2M, 1.44M, or 2.88M disk drives and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s, and 2 Mb/s. The W83977F/ AF provides two high-speed serial communication ports (UARTs), one of which supports serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability, and a processor interrupt system. Both UARTs provide legacy speed with baud rate 115.2k and provide advanced speed with baud rate 230k, 460k, and 921k bps which support higher speed modems. W83977AF alone provides independent 3rd UART (32-byte FIFO) dedicated for IR function. The W83977F/ AF supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP) and also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer port interface pins, also available are: Extension FDD Mode and Extension 2FDD Mode allowing one or two external floppy disk drives to be connected. The configuration registers support mode selection, function enable/disable, and power down function selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature demand of Windows 95TM, which makes system resource allocation more efficient than ever. W83977F/ AF provides functions that comply with ACPI (Advanced Configuration and Power Interface), which includes support of legacy and ACPI power management through SMI or SCI function pins. W83977F/ AF also has auto power management to reduce power consumption. The keyboard controller is based on 8042 compatible instruction set with a 2K Byte programmable ROM and a 256-Byte RAM bank. Keyboard BIOS firmware is available with optional AMIKEYTM -2, TM Phoenix MultiKey/42 , or customer code. The W83977F/ AF provides a set of flexible I/O control functions to the system designer through a set of General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured to provide a pre-defined alternate function. W83977F/ AF is made to fully comply with MicrosoftTM PC97 Hardware Design Guide. IRQs, DMAs, and I/O space resource are flexible to adjust to meet ISA PnP requirement. Full 16-bit address decoding is also provided. Moreover W83977F/ AF is made to meet the specification of PC97`s requirement in the power management: ACPI and DPM (Device Power Management).
Publication Release Date: March 1998 -1Revision 0.58
W83977F/ W83977AF
PRELIMINARY
FEATURES
General
* Plug & Play 1.0A Compliant * Support 13 IRQs, 4 DMA channels, full 16-bit addresses decoding * Capable of ISA Bus IRQ Sharing * Compliant with Microsoft PC97 Hardware Design Guide * Support DPM (Device Power Management), ACPI * Programmable configuration settings * 24 or 14.318 Mhz clock input
FDC
* Compatible with IBM PC AT disk drive systems * Variable write pre-compensation with track selectable capability * Support vertical recording format * DMA enable logic * 16-byte data FIFOs * Support floppy disk drives and tape drives * Detects all overrun and underrun conditions * Built-in address mark detection circuit to simplify the read electronics * FDD anti-virus functions with software write protect and FDD write enable signal (write data signal was forced to be inactive) * Support up to four 3.5-inch or 5.25-inch floppy disk drives * Completely compatible with industry standard 82077 * 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate * Support 3-mode FDD, and its Win95 driver
UART
* Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs * 3rd UART with 32-byte send/receive FIFO is supported for IR function [W83977AF only] * MIDI compatible * Fully programmable serial-interface characteristics: --- 5, 6, 7 or 8-bit characters --- Even, odd or no parity bit generation/detection --- 1, 1.5 or 2 stop bits generation * Internal diagnostic capabilities: --- Loop-back controls for communications link fault isolation --- Break, parity, overrun, framing error simulation * Programmable baud generator allows division of 1.8461 Mhz and 24 Mhz by 1 to (216-1) * Maximum baud rate up to 921k bps for 14.769 Mhz and 1.5M bps for 24 Mhz Publication Release Date: March 1998 -2Revision 0.58
W83977F/ W83977AF
PRELIMINARY
Infrared
* Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps * Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps * Support IrDA version 1.1 MIR (1.152M bps) and FIR (4M bps) protocol [W83977AF only] --- Single DMA channel for transmitter or receiver --- 3rd UART with 32-byte FIFO is supported in both TX/RX transmission [W83977AF only] --- 8-byte status FIFO is supported to store received frame status (such as overrun CRC error, etc.) * Support auto-config SIR and FIR [W83977AF only]
Parallel Port
* Compatible with IBM parallel port * Support PS/2 compatible bi-directional parallel port * Support Enhanced Parallel Port (EPP) - Compatible with IEEE 1284 specification * Support Extended Capabilities Port (ECP) - Compatible with IEEE 1284 specification * Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A and B through parallel port * Enhanced printer port back-drive current protection
Advanced Power Management (APM) Controlling
* Power turned on when RTC reaches a preset date and time * Power turned on when a ring pulse or pulse train is detected on the PHRI, or when a high to low transition on PWAKIN1, or PWAKIN2 input signals * Power turned on when PANSW input signal indicates a switch on event * Power turned off when PANSW input signal indicates a switch off event * Power turned off when a fail-safe event occurs (power-save mode detected but system is hung up) * Power turned off when software issues a power off command
Keyboard Controller
* 8042 based with optional F/W from AMIKKEY
TM
-2, Phoenix MultiKey/42
TM
or customer code
with 2K bytes of programmable ROM, and 256 bytes of RAM * Asynchronous Access to Two Data Registers and One status Register * Software compatibility with the 8042 and PC87911 microcontrollers * Support PS/2 mouse * Support port 92 * Support both interrupt and polling modes * Fast Gate A20 and Hardware Keyboard Reset * 8 Bit Timer/ Counter; support binary and BCD arithmetic * 6, 8, 12, or 16 Mhz operating frequency (16 Mhz available only if input clock rate = 14.318 Mhz)
Publication Release Date: March 1998 -3 Revision 0.58
W83977F/ W83977AF
PRELIMINARY
Real Time Clock
* * * * * * * *
27 bytes of clock, On-Now, and control/status register (14 bytes in Bank 0 and 13 bytes in Bank 2); 242 bytes of general purpose RAM BCD or Binary representation of time, calendar, and alarm registers Counts seconds, minutes, hours, days of week, days of month, month, year, and century 12-hour/ 24-hour clock with AM/PM in 12-hour mode Daylight saving time option; automatic leap-year adjustment Dedicated alarm (Alarm B) for On-Now function Programmable delay-time between panel switch off and power supply control Software control power-off; various and maskable events to activate system Power-On
* System Management Interrupt ( SMI ) for panel switch power-off event
General Purpose I/O Ports
* 14 programmable general purpose I/O ports; 6 dedicate, 8 optional * General purpose I/O ports can serve as simple I/O ports, interrupt steering inputs, watching dog timer output, power LED output, infrared I/O pins, general purpose address decoder, KBC control I/O pins.
Package
* 128-pin PQFP
Publication Release Date: March 1998 -4Revision 0.58
W83977F/ W83977AF
PRELIMINARY
PIN CONFIGURATION
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/ R I B
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IRQ14/GP14 IRQ15/GP15 IOR IOW AEN IOCHRDY D0 D1 D2 D3 D4 D5 VCC D6 D7 MR DACK0/GP16 VSS DRQ0/GP17 DACK1 DRQ1 DACK2 DRQ2 DACK3 DRQ3 TC
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
1 1 1 11 1 1 1 1 1 2 2 22 2 22 2 2 2 3 33 3 3 33 33 1 2 3 4 5 67 8 90 1 2 34 5 6 7 8 9 0 1 23 4 56 7 8 9 0 12 3 4 56 78
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
VBAT XTAL1 VSS XTAL2 MDATA KDATA KBLOCK/GP13 KBRST/GP12 GA20/GP11 VCC DCDB SOUTB SINB DTRB/ENCPNP RTSB/PENPLL DSRB CTSB DCDA SOUTA/PENKRC SINA DTRA/PNPCSV RTSA/HEFRAS DSRA CTSA CIRRX/GP24 IRRXH/IRSL0
C L K I N
D R V D E N 0
D/ / / / / / / / R D H R W T WW S VS E DP R E D T DK A A A E ECDT K P NH A 0 1G , G P 1 0
/ D I R
// MD OS BA
/ D S B
/ M O A
/ S PV B / PPV P P P PP P / / / I L E C U A DD S D D D D D D S I E NC C S C 7 6 S 5 4 3 2 1 0 L N R IIR DT YK E NT X
// AS FT DB
I R R X
I R T X
Publication Release Date: March 1998 -5 Revision 0.58
W83977F/ W83977AF
PRELIMINARY
1. PIN DESCRIPTION
Note: Please refer to Section 11.2 DC CHARACTERISTICS for details. I/O6t I/O8t I/O8 I/O12t I/O12 I/O16u - TTL level bi-directional pin with 6 mA source-sink capability - TTL level bi-directional pin with 8 mA source-sink capability - CMOS level bi-directional pin with 8 mA source-sink capability - TTL level bi-directional pin with 12 mA source-sink capability - CMOS level bi-directional pin with 12 mA source-sink capability - CMOS level bi-directional pin with 16 mA source-sink capability with internal pull-up resistor
I/OD16u - CMOS level bi-directional pin open drain output with 16 mA sink capability with internal pull-up resistor I/O24t OUT8t OUT12t OD12 OD24 INt INc INcu INcs INts INtsu - TTL level bi-directional pin with 24 mA source-sink capability - TTL level output pin with 8 mA source-sink capability - TTL level output pin with 12 mA source-sink capability - Open-drain output pin with 12 mA sink capability - Open-drain output pin with 24 mA sink capability - TTL level input pin - CMOS level input pin - CMOS level input pin with internal pull-up resitor - CMOS level Schmitt-triggered input pin - TTL level Schmitt-triggered input pin - TTL level Schmitt-triggered input pin with internal pull-up resistor
1.1 Host Interface
SYMBOL A0-A10 A11-A14 A15 D0-D5 D6-D7
IOR IOW
PIN 74-84 86-89 91 109-114 116-117 105 106 107 108 118
I/O INt INt INt I/O12t I/O12t INts INts INt OD24 INts
FUNCTION System address bus bits 0-10 System address bus bits 11-14 System address bus bit 15 System data bus bits 0-5 System data bus bits 6-7 CPU I/O read signal CPU I/O write signal System address bus enable In EPP Mode, this pin is the IO Channel Ready output to extend the host read/write cycle. Master Reset. Active high. MR is low during normal operations.
AEN IOCHRDY MR
Publication Release Date: March 1998 -6Revision 0.58
W83977F/ W83977AF
PRELIMINARY
1.1 Host Interface, continued
SYMBOL DACK0 GP16 (WDTO) P15 RTSC DRQ0 GP17 (PLEDO) P14 DTRC DACK1 DRQ1 DACK2 DRQ2 DACK3 DRQ3 TC IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8/ nIRQ8 IRQ9 IRQ10 IRQ11 IRQ12
PIN 119
I/O INts I/O12t I/O12t OUT12t
FUNCTION CR2C bit5, 4= 00 (default): DMA Channel 0 Acknowledge signal. CR2C bit5, 4= 01: General purpose I/O port 1 bit 6. It can be configured as a watchdog timer output. CR2C bit5, 4= 10: Keyboard P15 I/O port. CR2C bit5, 4= 11: RTS output of UART C. [W83977AF only]
121
OUT12t I/O12t I/O12t OUT12t
CR2C bit7, 6= 00 (default): DMA Channel 0 request signal. CR2C bit7, 6= 01: General purpose I/O port 1, bit 7. It can be configured as power LED output. CR2C bit7, 6= 10: Keyboard P14 I/O port. CR2C bit7, 6= 11: DTR output of UART C. [W83977AF only] DMA Channel 1 Acknowledge signal DMA Channel 1 request signal DMA Channel 2 Acknowledge signal DMA Channel 2 request signal DMA Channel 3 Acknowledge signal DMA Channel 3 request signal Terminal Count. When active, this pin indicates termination of a DMA transfer. Interrupt request 1 Interrupt request 3 Interrupt request 4 Interrupt request 5 Interrupt request 6 Interrupt request 7 Interrupt request 8; default is nIRQ8 for RTC Interrupt request 9 Interrupt request 10 Interrupt request 11 Interrupt request 12
122 123 124 125 126 127 128 99 98 97 96 95 94 93 92 100 101 102
INts OUT12t INts OUT12t INts OUT12t INts OUT12t OUT12t OUT12t OUT12t OUT12t OUT12t OUT12t OUT12t OUT12t OUT12t OUT12t
Publication Release Date: March 1998 -7 Revision 0.58
W83977F/ W83977AF
PRELIMINARY
1.1 Host Interface, continued
SYMBOL IRQ14 GP14 ( GPACS ) PLED IRSL1 IRQ15 GP15 ( GPAWE ) WDT IRSL2 CLKIN
PIN 103
I/O OUT12t I/O12t OUT12t OUT12t
FUNCTION CR2C bit1, 0= 00 (default): Interrupt request 14 CR2C bit1, 0= 01: General purpose I/O port 1, bit 4. It can be configured as a general purpose address decode output. CR2C bit1, 0= 10: Power LED output. CR2C bit1, 0= 11: IR module select signal 1. [W83977AF only] CR2C bit3, 2= 00 (default): Interrupt request 15 CR2C bit3, 2= 01: General purpose I/O port 1, bit 5. It can be configured as a general purpose address write enable output. CR2C bit3, 2= 10: Watch-Dog timer output. CR2C bit3, 2= 11: IR module select signal 2. [W83977AF only] 14.318/ 24 Mhz clock input, selectable through bit 5 of CR24.
104
OUT12t I/O12t OUT12t OUT12t
1
INt
1.2 Advanced Power Management
SYMBOL PHRI PIN 69 I/O INt FUNCTION CR2B bit2, 1=00 (default): Advanced Power Management (APM) phone ring indicator. Detection of an active PHRI pulse or pulse train activates the PSCTL signal. GP20 (KBRST) POFIRQ GP21 (P13) P16 RIC VSB PSCTL 71 72 70 I/O12t OUT12t I/O12t I/O12t INt OUT12t CR2B bit2, 1=01: General purpose I/O port 2, bit 0. It can be configured as keyboard reset (Keyboard P20). CR2B bit4, 3=00 (default): Advanced Power Management (APM) power off interrupt request. CR2B bit4, 3=01: General purpose I/O port 2, bit 1. It can be configured as Keyboard P13 I/O port. CR2B bit4, 3=10: Keyboard P16 I/O port. CR2B bit4, 3=11: RI input of UART C. [W83977AF only] Advanced Power Management (APM) standby current source CR2B bit5=0 (default): On/Off control for Advanced Power Management (APM). This signal tells the main power supply whether power should be turned on. CR2B bit5=1: General purpose I/O port 2, bit 2. It can be configured as Keyboard P14 I/O port.
GP22 (P14)
I/O12t
Publication Release Date: March 1998 -8Revision 0.58
W83977F/ W83977AF
PRELIMINARY
1.2 Advanced Power Management, continued
SYMBOL PANSW
PIN 73
I/O INt
FUNCTION CR2B bit7, 6=00 (default): On/Off switch for Advanced Power Management (APM). This signal indicates a request to switch the power on or off. When the VDD of the chip is disrupted, a high to low transition on this pin indicates a switch on request. When VDD returns, a high to low transition on this pin indicates a switch off request. CR2B bit7, 6=01: General purpose I/O port 2, bit 3. It can be configured as Keyboard P15 I/O port. CR2B bit7, 6=11: DCD input of UART C. [W83977AF only]
GP23 (P15) DCDC
I/O12t INt
1.3 Serial Port Interface
SYMBOL CTSA CTSB DSRA DSRB RTSA HEFRAS PIN 41 48 42 49 43 I/O8t INt I/O INt FUNCTION Clear To Send is the modem control input. The function of these pins can be tested by reading Bit 4 of the handshake status register. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. UART A Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. During power-on reset, this pin is pulled down internally and is defined as HEFRAS, which provides the power-on value for CR26 bit 6 (HEFRAS). A 4.7 k is recommended if intends to pull up. (select 370H as configuration I/O port address) 50 I/O8t UART B Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. During power-on reset, this pin is pulled down internally and is defined as nPENPLL, which provides the power-on value for CR24 bit 5 (ENPLL) and bit 6. A 4.7 k is recommended if intends to pull up. (PLL is disabled) 44 I/O8t UART A Data Terminal Ready. An active low signal informs the modem or data set that the controller is ready to communicate. During power-on reset, this pin is pulled down internally and is defined as PNPCSV , which provides the power-on value for CR24 bit 0 (PNPCSV ). A 4.7 k is recommended if intends to pull up. (clear the default value of FDC, UARTs, and PTR)
RTSB nPENPLL
DTRA PNPCSV
Publication Release Date: March 1998 -9 Revision 0.58
W83977F/ W83977AF
PRELIMINARY
1.3 Serial Port Interface, continued
SYMBOL DTRB ENCPNP
PIN 51
I/O I/O8t
FUNCTION UART B Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. During power-on reset, this pin is pulled down internally and is defined as ENCPNP, which provides the power-on value for CR24 bit 1 (ENPNP). A 4.7 k is recommended if intends to pull up. (enable comply PnP mode)
SINA SINB SOUTA PENKRC
45, 52 46
INt I/O8t
Serial Input. Used to receive serial data through the communication link. UART A Serial Output. Used to transmit serial data out to the communication link. During power-on reset, this pin is pulled down internally and is defined as PENKRC, which provides the power-on value for CR24 bit 2 (ENKBRTC). A 4.7 k is recommended if intends to pull up. (enable KBC and RTC)
SOUTB
53 47 54 65 66
I/O8t INt INt
UART B Serial Output. Used to transmit serial data out to the communication link. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set.
DCDA DCDB RIA RIB
1.4 Infrared Interface
SYMBOL IRRX (SINC) IRTX (SOUTC) IRRXH IRSL0 GP25 (GA20) CTSC CIRRX GP24 (P16) P13 PIN 37 38 39 I/O INcs OUT12t I/O12t OUT12t I/O12t INt 40 INt I/O12t I/O12t FUNCTION Infrared Receiver input. It functions as SIN input if UART C is configured as a simple serial port. [W83977AF only] Infrared Transmitter Output. It functions as SOUT output if UART C is configured as a simple serial port. [W83977AF only] CR2A bit3, 2=00 (default): High speed IR receiving terminal. CR2A bit3, 2=01: IR module select 0. CR2A bit3, 2=10: General purpose I/O port 2, bit 5. It can be configured as GATE A20 (Keyboard P21). CR2A bit3, 2=11: CTS input of UART C. [W83977AF only] CR2A bit5, 4=00 (default): Consumer IR receiving terminal. CR2A bit5, 4=01: General purpose I/O port 2, bit 4. It can be configured as Keyboard P16 I/O port. CR2A bit5, 4=10: Keyboard P13 I/O
Publication Release Date: March 1998 -10Revision 0.58
W83977F/ W83977AF
PRELIMINARY
1.5 Multi-Mode Parallel Port
The following pins have alternate functions, which are controlled by CR28 and L3-CRF0. SYMBOL SLCT PIN 18 I/O INt PRINTER MODE: SLCT An active high input on this pin indicates that the printer is selected. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. OD12 EXTENSION FDD MODE: WE2 This pin is for Extension FDD B; its function is the same as the WE pin of FDC. OD12 EXTENSION 2FDD MODE: WE2 This pin is for Extension FDD A and B; its function is the same as the WE pin of FDC. PE 19 INt PRINTER MODE: PE An active high input on this pin indicates that the printer has detected the end of the paper. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. OD12 EXTENSION FDD MODE: WD2 This pin is for Extension FDD B; its function is the same as the WD pin of FDC. OD12 EXTENSION 2FDD MODE: WD2 This pin is for Extension FDD A and B; its function is the same as the WD pin of FDC. BUSY 21 INt PRINTER MODE: BUSY An active high input indicates that the printer is not ready to receive data. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. OD12 EXTENSION FDD MODE: MOB2 This pin is for Extension FDD B; the function of this pin is the same as the MOB pin of FDC. OD12 EXTENSION 2FDD MODE: MOB2 This pin is for Extension FDD A and B; the function of this pin is the same as the MOB pin of FDC. FUNCTION
Publication Release Date: March 1998 -11 Revision 0.58
W83977F/ W83977AF
PRELIMINARY
1.5 Multi-Mode Parallel Port, continued
SYMBOL ACK
PIN 22
I/O INt PRINTER MODE: ACK
FUNCTION
An active low input on this pin indicates that the printer has received data and is ready to accept more data. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. OD12 EXTENSION FDD MODE: DSB2 This pin is for the Extension FDD B; its functions is the same as the DSB pin of FDC. OD12 EXTENSION 2FDD MODE: DSB2 This pin is for Extension FDD A and B; it functions is the same as the DSB pin of FDC. ERR 34 INt PRINTER MODE: ERR An active low input on this pin indicates that the printer has encountered an error condition. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. OD12 EXTENSION FDD MODE: HEAD2 This pin is for Extension FDD B; its function is the same as the HEADpin of FDC. OD12 EXTENSION 2FDD MODE: HEAD2 This pin is for Extension FDD A and B; its function is the same as the HEAD pin of FDC. SLIN 32 OD12 PRINTER MODE: SLIN Output line for detection of printer selection. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. OD12 EXTENSION FDD MODE: STEP2 This pin is for Extension FDD B; its function is the same as the STEP pin of FDC. OD12 EXTENSION 2FDD MODE: STEP2 This pin is for Extension FDD A and B; its function is the same as the STEP pin of FDC.
Publication Release Date: March 1998 -12Revision 0.58
W83977F/ W83977AF
PRELIMINARY
1.5 Multi-Mode Parallel Port, continued
SYMBOL INIT
PIN 33
I/O OD12 PRINTER MODE: INIT
FUNCTION
Output line for the printer initialization. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. OD12 EXTENSION FDD MODE: DIR2 This pin is for Extension FDD B; its function is the same as the DIR pin of FDC. OD12 EXTENSION 2FDD MODE: DIR2 This pin is for Extension FDD A and B; its function is the same as the DIR pin of FDC. AFD 35 OD12 PRINTER MODE: AFD An active low output from this pin causes the printer to auto feed a line after a line is printed. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. OD12 EXTENSION FDD MODE: DRVDEN0 This pin is for Extension FDD B; its function is the same as the DRVDEN0 pin of FDC. OD12 EXTENSION 2FDD MODE: DRVDEN0 This pin is for Extension FDD A and B; its function is the same as the DRVDEN0 pin of FDC. PRINTER MODE: STB An active low output is used to latch the parallel data into the printer. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. PD0 31 I/O24t EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: This pin is a tri-state output. PRINTER MODE: PD0 Parallel port data bus bit 0. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. INt EXTENSION FDD MODE: INDEX2 This pin is for Extension FDD B; the function of this pin is the same as the INDEX pin of FDC. It is pulled high internally. INt EXTENSION 2FDD MODE: INDEX2 This pin is for Extension FDD A and B; the function of this pin is the same as the INDEX pin of FDC. It is pulled high internally.
STB
36
OD12
Publication Release Date: March 1998 -13 Revision 0.58
W83977F/ W83977AF
PRELIMINARY
1.5 Multi-Mode Parallel Port, continued
SYMBOL PD1
PIN 30
I/O I/O24t PRINTER MODE: PD1
FUNCTION Parallel port data bus bit 1. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. .
INt
EXTENSION FDD MODE: TRAK02 This pin is for Extension FDD B; the function of this pin is the same as the TRAK0 pin of FDC. It is pulled high internally..
INt
EXTENSION. 2FDD MODE: TRAK02 This pin is for Extension FDD A and B; the function of this pin is the same as the TRAK0 pin of FDC. It is pulled high internally.
PD2
29
I/O24t
PRINTER MODE: PD2 Parallel port data bus bit 2. Refer to description of the parallel port for definition of this pin in ECP and EPP mode..
INt
EXTENSION FDD MODE: WP2 This pin is for Extension FDD B; the function of this pin is the same as the WP pin of FDC. It is pulled high internally.
INt
EXTENSION. 2FDD MODE: WP2 This pin is for Extension FDD A and B; the function of this pin is the same as the WP pin of FDC. It is pulled high internally.
PD3
28
I/O24t
PRINTER MODE: PD3 Parallel port data bus bit 3. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: RDATA2 This pin is for Extension FDD B; the function of this pin is the same as the RDATA pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE: RDATA2 This pin is for Extension FDD A and B; this function of this pin is the same as the RDATA pin of FDC. It is pulled high internally.
INt
INt
Publication Release Date: March 1998 -14Revision 0.58
W83977F/ W83977AF
PRELIMINARY
1.5 Multi-Mode Parallel Port, continued
SYMBOL PD4
PIN 27
I/O I/O24t
FUNCTION PRINTER MODE: PD4 Parallel port data bus bit 4. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: DSKCHG2 This pin is for Extension FDD B; the function of this pin is the same as the DSKCHG pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE: DSKCHG2 This pin is for Extension FDD A and B; this function of this pin is the same as the DSKCHG pin of FDC. It is pulled high internally. PRINTER MODE: PD5 Parallel port data bus bit 5. Refer to description of the parallel port for definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: This pin is a tri-state output. PRINTER MODE: PD6 Parallel port data bus bit 6. Refer to description of the parallel port for definition of this pin in ECP and EPP mode.
INt
INt
PD5
26
I/O24t
PD6 24 I/O24t
OD24
EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION. 2FDD MODE: MOA2 This pin is for Extension FDD A; its function is the same as the MOA pin of FDC.
PD7
23
I/O24t
PRINTER MODE: PD7 Parallel port data bus bit 7. Refer to description of the parallel port for definition of this pin in ECP and EPP mode.
OD24
EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: DSA2 This pin is for Extension FDD A; its function is the same as the DSA pin of FDC.
Publication Release Date: March 1998 -15 Revision 0.58
W83977F/ W83977AF
PRELIMINARY
1.6 FDC Interface
SYMBOL DRVDEN0 DRVDEN1 GP10 (IRQIN1) P12 DSRC HEAD WE WD STEP DIR MOB DSA DSB MOA DSKCHG 5 9 10 11 12 13 14 15 16 4 OD24 OD24 OD24 OD24 OD24 OD24 OD24 OD24 OD24 INcs PIN 2 3 I/O OD24 OD24 FUNCTION Drive Density Select bit 0. Drive Density Select bit 1. Alternate Function 1: General purpose I/O port 1, bit 0. It can be configured as an interrupt channel. Alternate Function 2: Keyboard P12 I/O port. Alternate Function 3: DSR input of UART C [W83977AF only] Head select. This open drain output determines which disk drive head is active. Logic 1 = side 0; open 0 = side 1 Write enable. An Logic drain output. Write data. This logic low open drain writes precompensation serial data to the selected FDD. An open drain output. Step output pulses. This active low open drain output produces a pulse to move the head to another track. Direction of the head step motor. An open drain output. Logic 1 = outward motion; Logic 0 = inward motion Motor B On. When set to 0, this pin enables disk drive 1. This is an open drain output. Drive Select A. When set to 0, this pin enables disk drive A. This is an open drain output. Drive Select B. When set to 0, this pin enables disk drive B. This is an open drain output. Motor A On. When set to 0, this pin enables disk drive 0. This is an open drain output. Diskette change. This signal is active low at power on and when the diskette is removed. This input pin is pulled up internally by a 1 K resistor, which can can be disabled by bit 7 of L0-CRF0 (FIPURDWN). The read data input signal from the FDD. This input pin is pulled up internally by a 1 K resistor, which can be disabled by bit 7 of L0CRF0 (FIPURDWN). Write protected. This active low Schmitt input from the disk drive indicates that the diskette is write-protected. This input pin is pulled up internally by a 1 K resistor, which can be disabled by bit 7 of L0CRF0 (FIPURDWN). Track 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the outermost track. This input pin is pulled up internally by a 1 K resistor, which can be disabled by bit 7 of L0-CRF0 (FIPURDWN).
RDATA
6
INcs
WP
7
INcs
TRAK0
8
INcs
Publication Release Date: March 1998 -16Revision 0.58
W83977F/ W83977AF
PRELIMINARY
1.6 FDC Interface, continued
SYMBOL INDEX
PIN 17
I/O INcs
FUNCTION This Schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. This input pin is pulled up internally by a 1 K resistor, which can be disabled by bit 7 of L0-CRF0 (FIPURDWN).
1.7 KBC Interface
SYMBOL KDATA MDATA KCLK MCLK GA20 GP11 (IRQIN2) KBRST GP12 (WDTO, IRRX) KBLOCK GP13 (PLEDO, IRTX) 58 57 PIN 59 60 67 68 56 I/O I/OD16u I/OD16u I/OD16u I/OD16u OUT12t I/O12t OUT12t I/O12t Keyboard Data PS2 Mouse Data Keyboard Clock PS2 Mouse Clock CR2A bit6= 0 (default): Keyboard GATE A20 (P21) Output. CR2A bit6= 1: General purpose I/O port 1, bit 1. configured as an interrupt channel. CR2A bit7= 0 (default): Keyboard Reset (P20) Output. CR2A bit7= 1: General purpose I/O port 1, bit 2. It can be configured as watchdog timer output or IRRX (SINC if UART C is used as a simple serial port [W83977AF only] ) input. CR2B bit0= 0 (default): Keyboard KINH (P17) Input. CR2B bit0= 1: General purpose I/O port 1, bit 3. It can be configured as watchdog timer output or IRTX (SOUTC if UART C is used as a simple serial port [W83977AF only] ) output. It can be FUNCTION
IN16tu I/O16tu
1.8 RTC Interface
SYMBOL VBAT XTAL1 XTAL2 PIN 64 63 61 INC O8t I/O RTC battery voltage input RTC 32.768Khz Clock Input RTC 32.768Khz Clock Output FUNCTION
1.9 POWER PINS
VCC GND 20,55, 85,115 25,62, 90,120 Ground +5V power supply for the digital circuitry
Publication Release Date: March 1998 -17 Revision 0.58
W83977F/ W83977AF
PRELIMINARY
2. FDC FUNCTIONAL DESCRIPTION
2.1 W83977F/ AF FDC
The floppy disk controller of the W83977F/ AF integrates all of the logic required for floppy disk control. The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible values. The FIFO provides better system performance in multi-master systems. The digital data separator supports up to 2 M bits/sec data rate. The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital Data Separator, FIFO, and FDC Core. 2.1.1 AT interface The interface consists of the standard asynchronous signals: RD , WR , A0-A3, IRQ, DMA control, and a data bus. The address lines select between the configuration registers, the FIFO and control/status registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal modes. The PS/2 register sets are a superset of the registers found in a PC/AT. 2.1.2 FIFO (Data) The FIFO is 16 bytes in size and has programmable threshold values. All command parameter information and disk data transfers go through the FIFO. Data transfers are governed by the RQM and DIO bits in the Main Status Register. The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware compatibility. The default values can be changed through the CONFIGURE command. The advantage of the FIFO is that it allows the system a larger DMA latency without causing disk errors. The following tables give several examples of the delays with a FIFO. The data are based upon the following formula: THRESHOLD # x (1/DATA/RATE) *8 - 1.5 S = DELAY FIFO THRESHOLD 1 Byte 2 Byte 8 Byte 15 Byte FIFO THRESHOLD 1 Byte 2 Byte 8 Byte 15 Byte Data Rate MAXIMUM DELAY TO SERVICING AT 500K BPS 1 x 16 S - 1.5 S = 14.5 S 2 x 16 S - 1.5 S = 30.5 S 8 x 16 S - 1.5 S = 6.5 S 15 x 16 S - 1.5 S = 238.5 S MAXIMUM DELAY TO SERVICING AT 1M BPS Data Rate 1 x 8 S - 1.5 S = 6.5 S 2 x 8 S - 1.5 S = 14.5 S 8 x 8 S - 1.5 S = 62.5 S 15 x 8 S - 1.5 S = 118.5 S
Publication Release Date: March 1998 -18Revision 0.58
W83977F/ W83977AF
PRELIMINARY
At the start of a command the FIFO is always disabled and command parameters must be sent based upon the RQM and DIO bit settings in the main status register. When the FDC enters the command execution phase, it clears the FIFO of any data to ensure that invalid data are not transferred. An overrun and underrun will terminate the current command and the data transfer. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered. DMA transfers are enabled with the SPECIFY command and are initiated by the FDC by activating the DRQ pin during a data transfer command. The FIFO is enabled directly by asserting DACK and addresses need not be valid. Note that if the DMA controller is programmed to function in verify mode a pseudo read is performed by the FDC based only on DACK . This mode is only available when the FDC has been configured into byte mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled the above operation is performed by using the new VERIFY command. No DMA operation is needed. @ 2.1.3 Data Separator The function of the data separator is to lock onto the incoming serial read data. When a lock is achieved the serial front end logic of the chip is provided with a clock which is synchronized to the read data. The synchronized clock, called the Data Window, is used to internally sample the serial data portion of the bit cell, and the alternate state samples the clock portion. Serial to parallel conversion logic separates the read data into clock and data bytes. The Digital Data Separator (DDS) has three parts: control logic, error adjustment, and speed tracking. The DDS circuit cycles once every 12 clock cycles ideally. Any data pulse input will be synchronized and then adjusted by immediate error adjustment. The control logic will generate RDD and RWD for every pulse input. During any cycle where no data pulse is present, the DDS cycles are based on speed. A digital integrator is used to keep track of the speed changes in the input data stream. 2.1.4 Write Precompensation The write precompensation logic is used to minimize bit shifts in the RDDATA stream from the disk drive. Shifting of bits is a known phenomenon in magnetic media and is dependent on the disk media and the floppy drive. The FDC monitors the bit stream that is being sent to the drive. The data patterns that require precompensation are well known. Depending upon the pattern, the bit is shifted either early or late relative to the surrounding bits. 2.1.5 Perpendicular Recording Mode The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular recording differs from the traditional longitudinal method in that the magnetic bits are oriented vertically. This scheme packs more data bits into the same area. FDCs with perpendicular recording drives can read standard 3.5" floppy disks and can read and write perpendicular media. Some manufacturers offer drives that can read and write standard and perpendicular media in a perpendicular media drive. A single command puts the FDC into perpendicular mode. All other commands operate as they normally do. The perpendicular mode requires a 1 Mbps data rate for the FDC. At this data rate the FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk.
Publication Release Date: March 1998 -19 Revision 0.58
W83977F/ W83977AF
PRELIMINARY
2.1.6 FDC Core The W83977F/ AF FDC is capable of performing twenty commands. Each command is initiated by a multi-byte transfer from the microprocessor. The result can also be a multi-byte transfer back to the microprocessor. Each command consists of three phases: command, execution, and result. Command The microprocessor issues all required information to the controller to perform a specific operation. Execution The controller performs the specified operation. Result After the operation is completed, status information and other housekeeping information is provided to the microprocessor. 2.1.7 FDC Commands Command Symbol Descriptions: C: Cylinder number 0 - 256 D: Data Pattern DIR: Step Direction DIR = 0, step out DIR = 1, step in DS0: Disk Drive Select 0 DS1: Disk Drive Select 1 DTL: Data Length EC: Enable Count EOT: End of Track EFIFO: Enable FIFO EIS: Enable Implied Seek EOT: End of track FIFOTHR: FIFO Threshold GAP: Gap length selection GPL: Gap Length H: Head number HDS: Head number select HLT: Head Load Time HUT: Head Unload Time LOCK: Lock EFIFO, FIFOTHR, PTRTRK bits prevent affected by software reset MFM: MFM or FM Mode MT: Multitrack N: The number of data bytes written in a sector NCN: New Cylinder Number ND: Non-DMA Mode OW: Overwritten Publication Release Date: March 1998 PCN: Present Cylinder Number -20Revision 0.58
W83977F/ W83977AF
PRELIMINARY
POLL: PRETRK: R: RCN: R/W: SC: SK: SRT: ST0: ST1: ST2: ST3: WG: Polling Disable Precompensation Start Track Number Record Relative Cylinder Number Read/Write Sector/per cylinder Skip deleted data address mark Step Rate Time Status Register 0 Status Register 1 Status Register 2 Status Register 3 Write gate alters timing of WE
Publication Release Date: March 1998 -21 Revision 0.58
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PRELIMINARY
(1) Read Data PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after command execution D7 0 D6 0 D5 SK 0 D4 0 0 D3 0 0 D2 1 D1 1 D0 0 REMARKS Command codes Sector ID information prior to command execution
MT MFM
HDS DS1 DS0
---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL -----------------------
Data transfer between the FDD and system Status information after command execution
Publication Release Date: March 1998 -22Revision 0.58
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PRELIMINARY
(2) Read Deleted Data PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after command execution D7 D6 D5 SK 0 D4 0 0 D3 1 0 D2 1 D1 0 D0 0 REMARKS Command codes
MT MFM 0 0
HDS DS1 DS0 Sector ID information prior to command execution
---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL -----------------------
Data transfer between the FDD and system Status information after command execution
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PRELIMINARY
(3) Read A Track PHASE Command R/W W W W W W W W W W Execution D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 0 0 D2 0 D1 1 D0 0 REMARKS Command codes
HDS DS1 DS0 Sector ID information prior to command execution
---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL -----------------------
Data transfer between the FDD and system; FDD reads contents of all cylinders from index hole to EOT R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after command execution Status information after command execution
Result
Publication Release Date: March 1998 -24Revision 0.58
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PRELIMINARY
(4) Read ID PHASE Command Execution R/W W W D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 1 0 D2 0 D1 1 D0 0 REMARKS Command codes The first correct ID information on the cylinder is stored in Data Register R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Disk status after the command has been completed Status information after command execution
HDS DS1 DS0
Result
(5) Verify PHASE Command R/W W W W W W W W W Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after command execution D7 EC D6 0 D5 0 D4 1 0 D3 0 0 D2 1 D1 1 D0 0 REMARKS Command codes Sector ID information prior to command execution
MT MFM SK
HDS DS1 DS0
---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL/SC -------------------
No data transfer takes place Status information after command execution
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PRELIMINARY
(6) Version PHASE Command Result (7) Write Data PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after Command execution D7 0 D6 0 D5 0 0 D4 0 0 D3 0 0 D2 1 D1 0 D0 1 REMARKS Command codes Sector ID information prior to Command execution R/W W R D7 0 1 D6 0 0 D5 0 0 D4 1 1 D3 0 0 D2 0 0 D1 0 0 D0 0 0 REMARKS Command code Enhanced controller
MT MFM
HDS DS1 DS0
---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL -----------------------
Data transfer between the FDD and system Status information after Command execution
Publication Release Date: March 1998 -26Revision 0.58
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PRELIMINARY
(8) Write Deleted Data PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after command execution D7 0 D6 0 D5 0 0 D4 0 0 D3 1 0 D2 0 D1 0 D0 1 REMARKS Command codes Sector ID information prior to command execution
MT MFM
HDS DS1 DS0
---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL -----------------------
Data transfer between the FDD and system Status information after command execution
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PRELIMINARY
(9) Format A Track PHASE Command R/W W W W W W W Execution for Each Sector Repeat: Result W W W W R R R R R R R D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 1 0 D2 1 D1 0 D0 1 REMARKS Command codes Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters
HDS DS1 DS0
---------------------- N -------------------------------------------- SC ------------------------------------------- GPL ------------------------------------------ D --------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------- Undefined ---------------------------------- Undefined ---------------------------------- Undefined ---------------------------------- Undefined -------------------
Status information after command execution
(10) Recalibrate PHASE Command Execution R/W W W D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 1 0 D1 1 D0 1 REMARKS Command codes Head retracted to Track 0 Interrupt
DS1 DS0
(11) Sense Interrupt Status PHASE Command Result R/W W R R D7 0 D6 0 D5 0 D4 0 D3 1 D2 0 D1 0 D0 0 REMARKS Command code Status information at the end of each seek operation
---------------- ST0 ---------------------------------------- PCN -------------------------
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PRELIMINARY
(12) Specify PHASE Command R/W W W W (13) Seek PHASE Command R/W W W W Execution R D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 1 0 D2 1 D1 1 D0 1 REMARKS Command codes D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 1 D0 1 REMARKS Command codes
| ---------SRT ----------- | --------- HUT ---------- | |------------ HLT ----------------------------------| ND
HDS DS1 DS0 Head positioned over proper cylinder on diskette
-------------------- NCN -----------------------
(14) Configure PHASE Command R/W W W W W Execution (15) Relative Seek PHASE Command R/W W W W D7 1 0 D6 DIR 0 D5 0 0 D4 0 0 D3 1 0 D2 1 D1 1 D0 1 REMARKS Command codes D7 0 0 0 D6 0 0 D5 0 0 D4 1 0 D3 0 0 D2 0 0 D1 1 0 D0 1 0 REMARKS Configure information
EIS EFIFO POLL | ------ FIFOTHR ----| Internal registers written
| --------------------PRETRK ----------------------- |
HDS DS1 DS0
| -------------------- RCN ---------------------------- |
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PRELIMINARY
(16) Dumpreg PHASE Command Result R/W W R R R R R R R R R R PHASE Command R/W W W (18) Lock PHASE Command Result R/W W R D7 0 D6 0 D5 0 0 D4 1 LOCK D3 0 0 D2 1 0 D1 0 0 D0 0 0 REMARKS Command Code D7 0 D6 0 D5 0 D4 0 D3 1 D2 1 D1 1 D0 0 REMARKS Registers placed in FIFO
----------------------- PCN-Drive 0------------------------------------------ PCN-Drive 1 ----------------------------------------- PCN-Drive 2------------------------------------------ PCN-Drive 3 --------------------------SRT ------------------ | --------- HUT ------------------ HLT -----------------------------------| ND ------------------------ SC/EOT ---------------------LOCK 0 D3 D2 D1 D0 GAP WG 0 EIS EFIFO POLL | ------ FIFOTHR ------------------------------PRETRK ------------------------D7 0 OW D6 0 0 D5 0 D3 D4 1 D2 D3 0 D1 D2 0 D1 1 D0 0 REMARKS Command Code
(17) Perpendicular Mode
D0 GAP WG
LOCK 0
(19) Sense Drive Status PHASE Command Result R/W W W R D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 1 D1 0 D0 0 REMARKS Command Code Status information about disk drive
HDS DS1 DS0
---------------- ST3 -------------------------
(20) Invalid PHASE Command R/W W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Invalid codes (no operation- FDC goes to standby state) ST0 = 80H
------------- Invalid Codes -----------------
Result
R
-------------------- ST0 ----------------------
Publication Release Date: March 1998 -30Revision 0.58
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PRELIMINARY
2.2 Register Descriptions
There are several status, data, and control registers in W83977F/ AF. These registers are defined below: ADDRESS OFFSET base address + 0 base address + 1 base address + 2 base address + 3 base address + 4 base address + 5 base address + 7 REGISTER READ SA REGISTER SB REGISTER TD REGISTER MS REGISTER DT (FIFO) REGISTER DI REGISTER WRITE
DO REGISTER TD REGISTER DR REGISTER DT (FIFO) REGISTER CC REGISTER
2.2.1 Status Register A (SA Register) (Read base address + 0) This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows:
7 6 5 4 3 2 1 0
DIR WP INDEX HEAD TRAK0 STEP DRV2 INIT PENDING
INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output.
DRV2 (Bit 6): 0 1 A second drive has been installed A second drive has not been installed
STEP (Bit 5): This bit indicates the complement of STEP output. TRAK0 (Bit 4): This bit indicates the value of TRAK0 input.
Publication Release Date: March 1998 -31 Revision 0.58
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PRELIMINARY
HEAD (Bit 3): This bit indicates the complement of HEAD output. 0 1 side 0 side 1
INDEX (Bit 2): This bit indicates the value of INDEX output. WP (Bit 1): 0 1 disk is write-protected disk is not write-protected
DIR (Bit 0) This bit indicates the direction of head movement. 0 1 outward direction inward direction
In PS/2 Model 30 mode, the bit definitions for this register are as follows:
7 6 5 4 3 2 1 0
DIR WP INDEX HEAD TRAK0 STEP F/F DRQ INIT PENDING
INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output. DRQ (Bit 6): This bit indicates the value of DRQ output pin. STEP F/F (Bit 5): This bit indicates the complement of latched STEP output. TRAK0 (Bit 4): This bit indicates the complement of TRAK0 input. HEAD (Bit 3): Publication Release Date: March 1998 -32Revision 0.58
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PRELIMINARY
This bit indicates the value of HEAD output. 0 1 side 1 side 0
INDEX (Bit 2): This bit indicates the complement of INDEX output. WP (Bit 1): 0 1 disk is not write-protected disk is write-protected
DIR (Bit 0) This bit indicates the direction of head movement. 0 1 inward direction outward direction
Status Register B (SB Register) (Read base address + 1) This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows:
7 1 6 1 MOT EN A MOT EN B WE RDATA Toggle WDATA Toggle Drive SEL0 5 4 3 2 1 0
Drive SEL0 (Bit 5): This bit indicates the status of DO REGISTER bit 0 (drive select bit 0). WDATA Toggle (Bit 4): This bit changes state at every rising edge of the WD output pin. RDATA Toggle (Bit 3): This bit changes state at every rising edge of the RDATA output pin. WE (Bit 2): This bit indicates the complement of the WE output pin. MOT EN B (Bit 1) This bit indicates the complement of the MOB output pin. Publication Release Date: March 1998 -33 Revision 0.58
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PRELIMINARY
MOT EN A (Bit 0) This bit indicates the complement of the MOA output pin. In PS/2 Model 30 mode, the bit definitions for this register are as follows:
7 6 5 4 3 2 1 0
DSC DSD WE F/F RDATA F/F WD F/F DSA DSB DRV2
DRV2 (Bit 7): 0 1 A second drive has been installed A second drive has not been installed
DSB (Bit 6): This bit indicates the status of DSB output pin. DSA (Bit 5): This bit indicates the status of DSA output pin. WD F/F(Bit 4): This bit indicates the complement of the latched WD output pin at every rising edge of the WD output pin. RDATA F/F(Bit 3): This bit indicates the complement of the latched RDATA output pin . WE F/F (Bit 2): This bit indicates the complement of latched WE output pin. DSD (Bit 1): 0 Drive D has been selected 1 Drive D has not been selected DSC (Bit 0): 0 Drive C has been selected 1 Drive C has not been selected
Publication Release Date: March 1998 -34Revision 0.58
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PRELIMINARY
2.2.3 Digital Output Register (DO Register) (Write base address + 2) The Digital Output Register is a write-only register controlling drive motors, drive selection, DRQ/IRQ enable, and FDC resetting. All the bits in this register are cleared by the MR pin. The bit definitions are as follows:
7 6 5 4 3 2 1-0 Drive Select: 00 select drive A 01 select drive B 10 select drive C 11 select drive D Floppy Disk Controller Reset Active low resets FDC DMA and INT Enable Active high enable DRQ/IRQ Motor Enable A. Motor A on when active high Motor Enable B. Motor B on when active high Motor Enable C. Motor C on when active high Motor Enable D. Motor D on when active high
2.2.4 Tape Drive Register (TD Register) (Read base address + 3) This register is used to assign a particular drive number to the tape drive support mode of the data separator. This register also holds the media ID, drive type, and floppy boot drive information of the floppy disk drive. In normal floppy mode, this register includes only bit 0 and 1. The bit definitions are as follows:
7 X 6 X 5 X 4 X 3 X 2 X Tape sel 0 Tape sel 1 1 0
If three mode FDD function is enabled (EN3MODE = 1 in Logical Device 0 CRF0 bit:0), the bit definitions are as follows:
7 6 5 4 3 2 1 0
Tape Sel 0 Tape Sel 1 Floppy boot drive 0 Floppy boot drive 1 Drive type ID0 Drive type ID1 Media ID0 Media ID1
Publication Release Date: March 1998 -35 Revision 0.58
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PRELIMINARY
Media ID1 Media ID0 (Bit 7, 6): These two bits are read only. These two bits reflect the value of Logical Device 0 CRF1 bit 4,5. Drive type ID1 Drive type ID0 (Bit 5, 4): These two bits reflect two of the bits of Logical Device 0 CRF2. Which two bits are reflected depends on the last drive selected in the DO REGISTER. Floppy Boot drive 1, 0 (Bit 3, 2): These two bits reflect the value of Logical Device 0 CRF1 bit 7,6. Tape Sel 1, Tape Sel 0 (Bit 1, 0): These two bits assign a logical drive number to the tape drive. Drive 0 is not available as a tape drive and is reserved as the floppy disk boot drive. TAPE SEL 1 0 0 1 1 TAPE SEL 0 0 1 0 1 DRIVE SELECTED None 1 2 3
2.2.5 Main Status Register (MS Register) (Read base address + 4) The Main Status Register is used to control the flow of data between the microprocessor and the controller. The bit definitions for this register are as follows:
7 6 5 4 3 2 1 0
FDD 0 Busy, (D0B = 1), FDD number 0 is in the SEEK mode. FDD 1 Busy, (D1B = 1), FDD number 1 is in the SEEK mode. FDD 2 Busy, (D2B = 1), FDD number 2 is in the SEEK mode. FDD 3 Busy, (D3B = 1), FDD number 3 is in the SEEK mode. FDC Busy, (CB). A read or write command is in the process when CB = HIGH. Non-DMA mode, the FDC is in the non-DMA mode, this bit is set only during the execution phase in non-DMA mode. Transition to LOW state indicates execution phase has ended. DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor. If DIO = LOW then transfer is from processor to Data Register. Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor.
2.2.6 Data Rate Register (DR Register) (Write base address + 4) The Data Rate Register is used to set the transfer rate and write precompensation. The data rate of the FDC is programmed by the CC REGISTER for PC-AT and PS/2 Model 30 and PS/2 mode, and not by the DR REGISTER. The real data rate is determined by the most recent write to either of the DR REGISTER or CC REGISTER.
Publication Release Date: March 1998 -36Revision 0.58
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PRELIMINARY
7 6 5 0 DRATE0 DRATE1 PRECOMP0 PRECOMP1 PRECOMP2 POWER DOWN S/W RESET 4 3 2 1 0
S/W RESET (Bit 7): This bit is the software reset bit. POWER-DOWN (Bit 6): 0 FDC in normal mode 1 FDC in power-down mode PRECOMP2 PRECOMP1 PRECOMP0 (Bit 4, 3, 2): These three bits select the value of write precompensation. The following tables show the precompensation values for the combination of these bits. PRECOMP 210 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 PRECOMPENSATION DELAY 250K - 1 Mbps 2 Mbps Tape drive Default Delays 41.67 nS 83.34 nS 125.00 nS 166.67 nS 208.33 nS 250.00 nS 0.00 nS (disabled) Default Delays 20.8 nS 41.17 nS 62.5nS 83.3 nS 104.2 nS 125.00 nS 0.00 nS (disabled)
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PRELIMINARY
DATA RATE 250 KB/S 300 KB/S 500 KB/S 1 MB/S 2 MB/S
DEFAULT PRECOMPENSATION DELAYS 125 nS 125 nS 125 nS 41.67nS 20.8 nS
DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC and reduced write current control. 00 500 KB/S (MFM), 250 KB/S (FM), RWC = 1 01 300 KB/S (MFM), 150 KB/S (FM), RWC = 0 10 250 KB/S (MFM), 125 KB/S (FM), RWC = 0 11 1 MB/S (MFM), Illegal (FM), RWC = 1 The 2 MB/S data rate for Tape drive is only supported by setting 01 to DRATE1 and DRATE0 bits, as well as setting 10 to DRT1 and DRT0 bits which are two of the Configure Register CRF4 or CRF5 bits in logic device 0. Please refer to the function description of CRF4 or CRF5 and data rate table for individual data rates setting. 2.2.7 FIFO Register (R/W base address + 5) The Data Register consists of four status registers in a stack with only one register presented to the data bus at a time. This register stores data, commands, and parameters and provides diskette-drive status information. Data bytes are passed through the data register to program or obtain results after a command. In the W83977F/ AF, this register defaults to FIFO disabled mode after reset. The FIFO can change its value and enable its operation through the CONFIGURE command.
Publication Release Date: March 1998 -38Revision 0.58
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PRELIMINARY
Status Register 0 (ST0)
7-6 5 4 3 2 1-0
US1, US0 Drive Select: 00 Drive A selected 01 Drive B selected 10 Drive C selected 11 Drive D selected HD Head address: 1 Head selected 0 Head selected NR Not Ready: 1 Drive is not ready 0 Drive is ready EC Equipment Check: 1 When a fault signal is received from the FDD or the track 0 signal fails to occur after 77 step pulses 0 No error SE Seek end: 1 seek end 0 seek error IC Interrupt Code: 00 Normal termination of command 01 Abnormal termination of command 10 Invalid command issue 11 Abnormal termination because the ready signal from FDD changed state during command execution
Status Register 1 (ST1)
7 6 5 4 3 2 1 0
Missing Address Mark. 1 When the FDC cannot detect the data address mark or the data address mark has been deleted. NW (Not Writable). 1 If a write Protect signal is detected from the diskette drive during execution of write data. ND (No DATA). 1 If specified sector cannot be found during execution of a read, write or verifly data. Not used. This bit is always 0. OR (Over Rum). 1 If the FDC is not serviced by the host system within a certain time interval during data transfer. DE (data Error).1 When the FDC detects a CRC error in either the ID field or the data field. Not used. This bit is always 0. EN (End of track). 1 When the FDC tries to access a sector beyond the final sector of a cylinder.
Status Register 2 (ST2)
7 6 5 4 3 2 1 0
MD (Missing Address Mark in Data Field). 1 If the FDC cannot find a data address mark (or the address mark has been deleted) when reading data from the media 0 No error BC (Bad Cylinder) 1 Bad Cylinder 0 No error SN (Scan Not satisfied) 1 During execution of the Scan command 0 No error SH (Scan Equal Hit) 1 During execution of the Scan command, if the equal condition is satisfied 0 No error WC (Wrong Cylinder) 1 Indicates wrong Cylinder DD (Data error in the Data field) 1 If the FDC detects a CRC error in the data field 0 No error CM (Control Mark) 1 During execution of the read data or scan command 0 No error Not used. This bit is always 0
Publication Release Date: March 1998 -39 Revision 0.58
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PRELIMINARY
Status Register 3 (ST3)
7 6 5 4 3 2 1 0
US0 Unit Select 0 US1 Unit Select 1 HD Head Address TS Two-Side TO Track 0 RY Ready WP Write Protected FT Fault
2.2.8 Digital Input Register (DI Register) (Read base address + 7) The Digital Input Register is an 8-bit read-only register used for diagnostic purposes. In a PC/XT or AT only Bit 7 is checked by the BIOS. When the register is read, Bit 7 shows the complement of DSKCHG , while other bits of the data bus remain in tri-state. Bit definitions are as follows:
7 6 5 4 3 2 1 0
xxx
xxxx for hard disk controller x Reservedreadthethis register, these bits are in tri-state During a of
DSKCHG
In the PS/2 mode, the bit definitions are as follows:
7 6 1 5 1 4 1 3 1 HIGH DENS DRATE0 DRATE1 2 1 0
DSKCHG
DSKCHG (Bit 7): This bit indicates the complement of the DSKCHG input. Bit 6-3: These bits are always a logic 1 during a read.
Publication Release Date: March 1998 -40Revision 0.58
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PRELIMINARY
DRATE1 DRATE0 (Bit 2, 1): These two bits select the data rate of the FDC. Refer to the DR register bits 1 and 0 for the settings corresponding to the individual data rates. HIGH DENS (Bit 0): 0 500 KB/S or 1 MB/S data rate (high density FDD) 1 250 KB/S or 300 KB/S data rate In the PS/2 Model 30 mode, the bit definitions are as follows:
7 6 0 5 0 4 0 DRATE0 DRATE1 NOPREC DMAEN 3 2 1 0
DSKCHG
DSKCHG (Bit 7): This bit indicates the status of DSKCHG input. Bit 6-4: These bits are always a logic 1 during a read. DMAEN (Bit 3): This bit indicates the value of DO REGISTER bit 3. NOPREC (Bit 2): This bit indicates the value of CC REGISTER NOPREC bit. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC.
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PRELIMINARY
2.2.9 Configuration Control Register (CC Register) (Write base address + 7) This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as follows:
7 6 5 4 3 2 1 0
x
x
x
x
x
x
DRATE0 DRATE1
X: Reserved Bit 7-2: Reserved. These bits should be set to 0. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC. In the PS/2 Model 30 mode, the bit definitions are as follows:
7 X 6 X 5 X 4 X 3 X DRATE0 DRATE1 NOPREC 2 1 0
X: Reserved Bit 7-3: Reserved. These bits should be set to 0. NOPREC (Bit 2): This bit indicates no precompensation. It has no function and can be set by software. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC.
Publication Release Date: March 1998 -42Revision 0.58
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PRELIMINARY
3.
3.1
UART PORT
Universal Asynchronous Receiver/Transmitter (UART A, UART B)
The UARTs are used to convert parallel data into serial format on the transmit side and convert serial data to parallel format on the receiver side. The serial format, in order of transmission and reception, is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half (five-bit format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65535 and producing a 16x clock for driving the internal transmitter logic. Provisions are also included to use this 16x clock to drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore, the UARTs also include complete modem control capability and a processor interrupt system that may be software trailed to the computing time required to handle the communication link. The UARTs have a FIFO mode to reduce the number of interrupts presented to the CPU. In each UART, there are 16-byte FIFOs for both receive and transmit mode.
3.2
3.2.1
Register Address
UART Control Register (UCR) (Read/Write)
The UART Control Register controls and defines the protocol for asynchronous data communications, including data length, stop bit, parity, and baud rate selection.
7 6 5 4 3 2 1 0
Data length select bit 0 (DLS0) Data length select bit 1(DLS1) Multiple stop bits enable (MSBE) Parity bit enable (PBE) Even parity enable (EPE) Parity bit fixed enable (PBFE) Set silence enable (SSE) Baudrate divisor latch access bit (BDLAB)
Bit 7: BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit binary format) from the divisor latches of the baudrate generator during a read or write operation. When this bit is reset, the Receiver Buffer Register, the Transmitter Buffer Register, or the Interrupt Control Register can be accessed. Bit 6: SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only IRTX is affected by this bit; the transmitter is not affected. Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1, (1) if EPE is logical 1, the parity bit is fixed as logical 0 to transmit and check. (2) if EPE is logical 0, the parity bit is fixed as logical 1 to transmit and check.
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TABLE 3-1 UART Register Bit Map Bit Number
Register Address Base +0 BDLAB = 0 Receiver Buffer Register (Read Only) Transmitter Buffer Register (Write Only) Interrupt Control Register RBR 0 RX Data Bit 0 1 RX Data Bit 1 2 RX Data Bit 2 3 RX Data Bit 3 4 RX Data Bit 4 5 RX Data Bit 5 6 RX Data Bit 6 7 RX Data Bit 7
+0 BDLAB = 0 +1 BDLAB = 0
TBR
TX Data Bit 0
TX Data Bit 1 TBR Empty Interrupt Enable (ETBREI) Interrupt Status Bit (0) RCVR FIFO Reset Data Length Select Bit 1 (DLS1) Request to Send (RTS) Overrun Error (OER) DSR Toggling (TDSR) Bit 1 Bit 1 Bit 9
TX Data Bit 2 USR Interrupt Enable (EUSRI) Interrupt Status Bit (1) XMIT FIFO Reset Multiple Stop Bits Enable (MSBE) Loopback RI Input Parity Bit Error (PBER) RI Falling Edge (FERI) Bit 2 Bit 2 Bit 10
TX Data Bit 3 HSR Interrupt Enable (EHSRI) Interrupt Status Bit (2)** DMA Mode Select Parity Bit Enable (PBE) IRQ Enable
TX Data Bit 4 0
TX Data Bit 5 0
TX Data Bit 6 0
TX Data Bit 7 0
ICR
RBR Data Ready Interrupt Enable (ERDRI) "0" if Interrupt Pending FIFO Enable
+2
Interrupt Status Register (Read Only) UART FIFO Control Register (Write Only) UART Control Register
ISR
0
0
FIFOs Enabled **
FIFOs Enabled ** RX Interrupt Active Level (MSB) Baudrate Divisor Latch Access Bit (BDLAB) 0
+2
UFR
Reserved
Reversed
RX Interrupt Active Level (LSB) Set Silence Enable (SSE) 0
+3
UCR
Data Length Select Bit 0 (DLS0) Data Terminal Ready (DTR) RBR Data Ready (RDR)
Even Parity Enable (EPE) Internal Loopback Enable Silent Byte Detected (SBD) Clear to Send (CTS) Bit 4 Bit 4 Bit 12
Parity Bit Fixed Enable PBFE) 0
+4
Handshake Control Register UART Status Register
HCR
+5
USR
No Stop Bit Error (NSER) DCD Toggling (TDCD) Bit 3 Bit 3 Bit 11
TBR Empty (TBRE) Data Set Ready (DSR) Bit 5 Bit 5 Bit 13
TSR Empty (TSRE) Ring Indicator (RI) Bit 6 Bit 6 Bit 14
RX FIFO Error Indication (RFEI) ** Data Carrier Detect (DCD) Bit 7 Bit 7 Bit 15
+6
Handshake Status Register User Defined Register Baudrate Divisor Latch Low Baudrate Divisor Latch High
HSR
CTS Toggling (TCTS) Bit 0 Bit 0 Bit 8
+7 +0 BDLAB = 1 +1 BDLAB = 1
UDR BLL BHL
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received. **: These bits are always 0 in 16450 Mode.
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Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit 3 is programmed. When this bit is set, an even number of logic 1's are sent or checked. When the bit is reset, an odd number of logic 1's are sent or checked. Bit 3: PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT will be stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same position as the transmitter will be detected. Bit 2: MSBE. This bit defines the number of stop bits in each serial character that is transmitted or received. (1) If MSBE is set to a logical 0, one stop bit is sent and checked. (2) If MSBE is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent and checked. (3) If MSBE is set to a logical 1, and data length is 6, 7, or 8 bits, two stop bits are sent and checked. Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in each serial character.
TABLE 3-2 WORD LENGTH DEFINITION
DLS1 0 0 1 1
DLS0 0 1 0 1
DATA LENGTH 5 bits 6 bits 7 bits 8 bits
3.2.2
UART Status Register (USR) (Read/Write)
This 8-bit register provides information about the status of the data transfer during communication.
7 6 5 4 3 2 1 0
RBR Data ready (RDR) Overrun error (OER) Parity bit error (PBER) No stop bit error (NSER) Silent byte detected (SBD) Transmitter Buffer Register empty (TBRE) Transmitter Shift Register empty (TSRE) RX FIFO Error Indication (RFEI)
Bit 7: RFEI. In 16450 mode, this bit is always set to a logic 0. In 16550 mode, this bit is set to a logic 1 when there is at least one parity bit error, no stop bit error or silent byte detected in the FIFO. In 16550 mode, this bit is cleared by reading from the USR if there are no remaining errors left in the FIFO.
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Bit 6: TSRE. In 16450 mode, when TBR and TSR are both empty, this bit will be set to a logical 1. In 16550 mode, if the transmit FIFO and TSR are both empty, it will be set to a logical 1. Other thanthese two cases, this bit will be reset to a logical 0. Bit 5: TBRE. In 16450 mode, when a data character is transferred from TBR to TSR, this bit will be set to a logical 1. If ETREI of ICR is a logical 1, an interrupt will be generated to notify the CPU to write the next data. In 16550 mode, this bit will be set to a logical 1 when the transmit FIFO is empty. It will be reset to a logical 0 when the CPU writes data into TBR or FIFO. Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a full word time, including start bit, data bits, parity bit, and stop bits. In 16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0. Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. In 16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0. Bit 2: PBER. This bit is set to a logical 1 to indicate that the parity bit of received data is wrong. In 16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0. Bit 1: OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next received data before they were read by the CPU. In 16550 mode, it indicates the same condition instead of FIFO full. When the CPU reads USR, it will clear this bit to a logical 0. Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0. 3.2.3 Handshake Control Register (HCR) (Read/Write)
This register controls the pins of the UART used for handshaking peripherals such as modem, and controls the diagnostic mode of the UART.
7 0 6 0 5 0 Data terminal ready (DTR) Request to send (RTS) Loopback RI input IRQ enable Internal loopback enable 4 3 2 1 0
Bit 4: When this bit is set to a logical 1, the UART enters diagnostic mode by an internal loopback, as follows: (1) SOUT is forced to logical 1, and SIN is isolated from the communication link instead of the TSR. (2) Modem output pins are set to their inactive state. (3) Modem input pins are isolated from the communication link and connect internally as DTR
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(bit 0 of HCR) DSR, RTS ( bit 1 of HCR) CTS, Loopback RI input ( bit 2 of HCR) RI and IRQ enable ( bit 3 of HCR) DCD . Aside from the above connections, the UART operates normally. This method allows the CPU to test the UART in a convenient way. Bit 3: The UART interrupt output is enabled by setting this bit to a logic 1. In the diagnostic mode this bit is internally connected to the modem control input DCD . Bit 2: This bit is used only in the diagnostic mode. In the diagnostic mode this bit is internally connected to the modem control input RI . Bit 1: This bit controls the RTS output. The value of this bit is inverted and output to RTS . Bit 0: This bit controls the DTR output. The value of this bit is inverted and output to DTR . 3.2.4 Handshake Status Register (HSR) (Read/Write)
This register reflects the current state of four input pins for handshake peripherals such as a modem and records changes on these pins.
7 6 5 4 3 2 1 0
CTS toggling (TCTS) DSR toggling (TDSR) RI falling edge (FERI) DCD toggling (TDCD) Clear to send (CTS) Data set ready (DSR) Ring indicator (RI) Data carrier detect (DCD)
Bit 7: This bit is the opposite of the DCD input. This bit is equivalent to bit 3 of HCR in loopback mode. Bit 6: This bit is the opposite of the RI input. This bit is equivalent to bit 2 of HCR in loopback mode. Bit 5: This bit is the opposite of the DSR input. This bit is equivalent to bit 0 of HCR in loopback mode. Bit 4: This bit is the opposite of the CTS input. This bit is equivalent to bit 1 of HCR in loopback mode. Bit 3: TDCD. This bit indicates that the DCD pin has changed state after HSR was read by the CPU.
Bit 2: FERI. This bit indicates that the RI pin has changed from low to high state after HSR was read by the CPU. Bit 1: TDSR. This bit indicates that the DSR pin has changed state after HSR was read by the CPU. Bit 0: TCTS. This bit indicates that the CTS pin has changed state after HSR was read. 3.2.5 UART FIFO Control Register (UFR) (Write only)
This register is used to control the FIFO functions of the UART.
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7 6 5 4 3 2 1 0
FIFO enable Receiver FIFO reset Transmitter FIFO reset DMA mode select Reserved Reserved RX interrupt active level (LSB) RX interrupt active level (MSB)
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the receiver FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO. TABLE 3-3 FIFO TRIGGER LEVEL BIT 7 0 0 1 1 Bit 4, 5: Reserved Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if UFR bit 0 = 1. Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear to a logical 0 by itself after being set to a logical 1. Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to a logical 0 by itself after being set to a logical 1. Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before other bits of UFR are programmed. BIT 6 0 1 0 1 RX FIFO INTERRUPT ACTIVE LEVEL (BYTES) 01 04 08 14
3.2.6
Interrupt Status Register (ISR) (Read only)
This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3 bits.
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7 6 5 0 4 0 0 if interrupt pending Interrupt Status bit 0 Interrupt Status bit 1 Interrupt Status bit 2 FIFOs enabled FIFOs enabled 3 2 1 0
Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1. Bit 5, 4: These two bits are always logic 0. Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a timeout interrupt is pending. Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below. Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred, this bit will be set to a logical 0.
TABLE 3-4 INTERRUPT CONTROL FUNCTION ISR
Bit 3 0 0 Bit 2 0 1 Bit 1 0 1 Bit 0 1 0 Interrupt priority First Interrupt Type
INTERRUPT SET AND FUNCTION
Interrupt Source Clear Interrupt
UART Receive Status RBR Data Ready
No Interrupt pending 1. OER = 1 2. PBER =1 Read USR
-
3. NSER = 1 4. SBD = 1 1. RBR data ready 2. FIFO interrupt active level reached 1. Read RBR 2. Read RBR until FIFO data under active level Read RBR
0
1
0
0
Second
1
1
0
0
Second
FIFO Data Timeout
Data present in RX FIFO for 4 characters period of time since last access of RX FIFO. TBR empty
0
0
1
0
Third
TBR Empty
1. Write data into TBR 2. Read ISR (if priority is third)
0
0
0
0
Fourth
Handshake status
1. TCTS = 1 3. FERI = 1
2. TDSR = 1 4. TDCD = 1
Read HSR
** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
3.2.7
Interrupt Control Register (ICR) (Read/Write)
This 8-bit register allows the five types of controller interrupts to activate the interrupt output signal separately. The interrupt system can be totally disabled by resetting bits 0 through 3 of the Publication Release Date: January 1997 - 49 - Revision 0.50
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Interrupt
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Control Register (ICR). A selected interrupt can be enabled by setting the appropriate bits of this register to a logical 1.
7 0 6 0 5 0 4 0 RBR data ready interrupt enable (ERDRI) TBR empty interrupt enable (ETBREI) UART receive status interrupt enable (EUSRI) Handshake status interrupt enable (EHSRI) 3 2 1 0
Bit 7-4: These four bits are always logic 0. Bit 3: EHSRI. Setting this bit to a logical 1 enables the handshake status register interrupt. Bit 2: EUSRI. Setting this bit to a logical 1 enables the UART status register interrupt. Bit 1: ETBREI. Setting this bit to a logical 1 enables the TBR empty interrupt. Bit 0: ERDRI. Setting this bit to a logical 1 enables the RBR data ready interrupt. 3.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write)
Two 8-bit registers, BLL and BHL, compose a programmable baud generator that uses 24 MHz to 16 generate a 1.8461 MHz frequency and divides it by a divisor from 1 to 2 -1. The output frequency of the baud generator is the baud rate multiplied by 16, and this is the base frequency for the transmitter and receiver. The table in the next page illustrates the use of the baud generator with a frequency of 1.8461 MHz. In high-speed UART mode (refer to CR0C bit7 and CR0C bit6), the programmable baud generator directly uses 24 MHz and the same divisor as the normal speed divisor. In highspeed mode, the data transmission rate can be as high as 1.5M bps. 3.2.9 User-defined Register (UDR) (Read/Write)
This is a temporary register that can be accessed and defined by the user.
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TABLE 3-5 BAUD RATE TABLE BAUD RATE FROM DIFFERENT PRE-DIVIDER Pre-Div: 13 1.8461M Hz 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 Pre-Div:1.625 14.769M Hz 400 600 880 1076 1200 2400 4800 9600 14400 16000 19200 28800 38400 57600 76800 153600 307200 460800 921600 Pre-Div: 1.0 24M Hz 650 975 1430 1478.5 1950 3900 7800 15600 23400 26000 31200 46800 62400 93600 124800 249600 499200 748800 1497600 Decimal divisor used to generate 16X clock 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 1 Error Percentage between desired and actual ** ** 0.18% 0.099% ** ** ** ** ** 0.53% ** ** ** ** ** ** ** ** **
** The percentage error for all baud rates, except where indicated otherwise, is 0.16%. Note. Pre-Divisor is determined by CRF0 of UART A and B.
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4. INFRARED (IR) PORT
The Infrared (IR) function provides point-to-point (or multi-point to multi-point) wireless communication which can operate under various transmission protocols including IrDA 1.0 SIR, IrDA 1.1 MIR (1.152 Mbps), IrDA 1.1 FIR (4 Mbps), SHARP ASK-IR, and remote control (NEC, RC-5, advanced RC-5, and RECS-80 protocol).
4.1 IR Register Description
When bank select enable bit (ENBNKSEL, the bit 0 in CRF0 of logic device 6) is set, legacy IR will be switched to Advanced IR, and eight Register Sets can then be accessible. These Register Sets control enhanced IR, SIR, MIR, or FIR. Also a superior traditional SIR function can be used with enhanced features such as 32-byte transmitter/receiver FIFOs, non-encoding IRQ identify status register, and automatic flow control. The MIR/FIR and remote control registers are also defined in these Register Sets. Structure of these Register Sets is shown as follows.
Reg 7 Reg 6 Reg 5 Reg 4 BDL/SSR Reg 2 Reg 1 Reg 0
Set 0 Set 1 Set 2 Set 3 Set 4 Set 5 Set 6 Set 7
All in one Reg to Select SSR
*Set 0, 1 are legacy/Advanced UART Registers *Set 2~7 are Advanced UART Registers
Each of these register sets has a common register, namely Sets Select Register (SSR), in order to switch to another register set. The summary description of these Sets is shown in the following. Set 0 1 2 3 4 5 6 7 Sets Description Legacy/Advanced IR Control and Status Registers. Legacy Baud Rate Divisor Register. Advanced IR Control and Status Registers. Version ID and Mapped Control Registers. Transmitter/Receiver/Timer Counter Registers and IR Control Registers. Flow Control and IR Control and Frame Status FIFO Registers. IR Physical Layer Control Registers Remote Control and IR front-end Module Selection Registers.
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4.2 Set0-Legacy/Advanced IR Control and Status Registers
Address Offset 0 1 2 3 4 5 6 7 Register Name RBR/TBR ICR ISR/UFR UCR/SSR HCR USR HSR UDR/ESCR Register Description Receiver/Transmitter Buffer Registers Interrupt Control Register Interrupt Status or IR FIFO Control Register IR Control or Sets Select Register Handshake Control Register IR Status Register Handshake Status Register User Defined Register
4.2.1 Set0.Reg0 - Receiver/Transmitter Buffer Registers (RBR/TBR) (Read/Write) Receiver Buffer Register is read only and Transmitter Buffer Register is write only. When operate in the PIO mode, the port is used to Receive/Transmit 8-bit data. When function as a legacy IR, this port only supports PIO mode. If set in the advanced IR mode and configured as MIR/FIR/Remote IR, this port can support DMA transmission. Two DMA channels can be used simultaneously, one for TX DMA and the other for RX DMA. Therefore, single DMA channel is also supported when set the bit of D_CHSW (DMA Channel Swap, in Set2.Reg2.Bit3) and the TX/RX DMA channel is swapped. Note that two DMA channel can be defined in configure register CR2A which selects DMA channel or disables DMA channel. If only RX DMA channel is enabled while TX DMA channel is disabled, then the single DMA channel will be selected. 4.2.2 Set0.Reg1 - Interrupt Control Register (ICR) B2 B1 B0 EUSRI ETBREI ERDRI EUSRI/ ETBREI ERBRI TXURI The advanced IR functions including Advanced SIR/ASK-IR, MIR, FIR, or Remote IR are described as follows. Bit 7: Legacy IR Mode: Not used. A read will return 0. Advanced IR Mode: ETMRI - Enable Timer Interrupt A write to 1 will enable timer interrupt. Legacy IR Mode: Not used. A read will return 0. MIR, FIR mode: EFSFI - Enable Frame Status FIFO Interrupt A write to 1 will enable frame status FIFO interrupt. Advanced SIR/ASK-IR, Remote IR: Not used. Legacy IR Mode: Not used. A read will return 0. Advanced SIR/ASK-IR, MIR, FIR, Remote IR: ETXTHI - Enable Transmitter Threshold Interrupt A write to 1 will enable transmitter threshold interrupt. Mode Legacy IR Advanced IR B7 0 ETMRI B6 0 EFSFI B5 0 ETXTHI B4 0 EDMAI B3 0 0
Bit 6:
Bit 5:
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Bit 4: Legacy IR Mode: Not used. A read will return 0. MIR, FIR, Remote IR: EDMAI - Enable DMA Interrupt. A write to 1 will enable DMA interrupt. Reserved. A read will return 0. Legacy IR Mode: EUSRI - Enable USR (IR Status Register) Interrupt A write to 1 will enable IR status register interrupt. Advanced SIR/ASK-IR: EUSRI - Enable USR (IR Status Register) Interrupt A write to 1 will enable IR status register interrupt. MIR, FIR, Remote Controller: EHSRI/ETXURI - Enable USR Interrupt or Enable Transmitter Underrun Interrupt A write to 1 will enable USR interrupt or enable transmitter underrun interrupt. ETBREI - Enable TBR (Transmitter Buffer Register) Empty Interrupt A write to 1 will enable the transmitter buffer register empty interrupt. ERBRI - Enable RBR (Receiver Buffer Register) Interrupt A write to 1 will enable receiver buffer register interrupt.
Bit 3: Bit 2:
Bit 1: Bit 0:
4.2.3 Set0.Reg2 - Interrupt Status Register/IR FIFO Control Register (ISR/UFR) 4.2.3.1 Interrupt Status Register (Read Only) Mode Legacy IR Advanced IR
Reset Value
B7 B6 B5 B4 FIFO Enable FIFO Enable 0 0 TMR_I FSF_I TXTH_I DMA_I 0 0 1 0
B3 IID2 HS_I 0
B2 IID1 USR_I/ FEND_I 0
B1 B0 IID0 IP TXEMP_I RXTH_I 1 0
Legacy IR: This register reflects the Legacy IR interrupt status, which is encoded by different interrupt sources into 3 bits. Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1. Bit 5, 4: These two bits are always logical 0. Bit 3: When not in FIFO mode, this bit is always 0. In FIFO mode, both bit 3 and 2 are set to logical 1 when a time-out interrupt is pending. Bit 2, 1: These bits identify the priority level of the pending interrupt, as shown in the table below. Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred, this bit will be set to logical 0.
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TABLE: INTERRUPT CONTROL FUNCTION
ISR
Bit 3 0 0 Bit 2 0 1 Bit 1 0 1 Bit 0 1 0 Interrupt priority First Interrupt Type
INTERRUPT SET AND FUNCTION
Interrupt Source Clear Interrupt
IR Receive Status
No Interrupt pending 1. OER = 1 2. PBER =1 Read USR
-
3. NSER = 1 4. SBD = 1 0 1 0 0 Second RBR Data Ready 1. RBR data ready 2. FIFO interrupt active level reached 1 1 0 0 Second FIFO Data Time-out Data present in RX FIFO for 4 characters period of time since last access of RX FIFO. TBR empty 1. Read RBR 2. Read RBR until FIFO data under active level Read RBR
0
0
1
0
Third
TBR Empty
1. Write data into TBR 2. Read ISR (if priority is third)
** Bit 3 of ISR is enabled when bit 0 of UFR is a logical 1.
Advanced IR: Bit 7: TMR_I - Timer Interrupt. Set to 1 when timer count to logical 0. This bit is valid when: (1) the timer registers are defined in Set4.Reg0 and Set4.Reg1; (2) EN_TMR(Enable Timer, in Set4.Reg2.Bit0) is set to 1; (3) ENTMR_I (Enable Timer Interrupt, in Set0.Reg1.Bit7) is set to 1. Bit 6: MIR, FIR modes: FSF_I - Frame Status FIFO Interrupt. Set to 1 when Frame Status FIFO is equal or larger than the threshold level or Frame Status FIFO time-out occurs. Cleared to 0 when Frame Status FIFO is below the threshold level. Advanced SIR/ASK-IR, Remote IR modes: Not used. Bit 5: TXTH_I - Transmitter Threshold Interrupt. Set to 1 if the TBR (Transmitter Buffer Register) FIFO is below the threshold level. Cleared to 0 if the TBR (Transmitter Buffer Register) FIFO is above the threshold level. Bit 4: MIR, FIR, Remote IR Modes: DMA_I - DMA Interrupt. Set to 1 if the DMA controller 8237A sends a TC (Terminal Count) to I/O device which might be a Transmitter TC or a Receiver TC. Cleared to 0 when this register is read. Bit 3: HS_I - Handshake Status Interrupt. Set to 1 when the Handshake Status Register has a toggle. Cleared to 0 when Handshake Status Register (HSR) is read. Note that in all IR modes including SIR, ASKIR, MIR, FIR, and Remote Control IR, this bit defaults to be inactive unless IR Handshake Status Enable (IRHS_EN) is set to 1. Bit 2: Advanced SIR/ASK-IR modes: USR_I - IR Status Interrupt. Set to 1 when overrun error, parity error, stop bit error, or silent byte error detected and registered in the IR Status Register (USR). Cleared to 0 when USR is read. MIR, FIR modes: FEND_I - Frame End Interrupt. Set to 1 when (1) a frame has a grace end to be detected where the frame signal is defined in the physical layer of IrDA version 1.1; (2) abort signal or illegal signal has been detected during receiving valid data. Cleared to 0 when this register is read. Remote Controller Mode: Not used.
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Bit 1: TXEMP_I - Transmitter Empty. Set to 1 when transmitter (or, say, FIFO + Transmitter) is empty. Cleared to 0 when this register is read. RXTH_I - Receiver Threshold Interrupt. Set to 1 when (1) the Receiver Buffer Register (RBR) is equal or larger than the threshold level; or (2) RBR time-out occurs if the receiver buffer register has valid data and below the threshold level. Cleared to 0 when RBR is less than threshold level after reading RBR.
Bit 0:
4.2.3.2 IR FIFO Control Register (UFR): Mode Bit 7 Legacy IR RXFTL1 (MSB) Advanced RXFTL1 IR (MSB) Reset Value 0 Bit 6 RXFTL0 (LSB) RXFTL0 (LSB) 0 Bit 5 0 TXFTL1 (MSB) 0 Bit 4 0 TXFTL0 (LSB) 0 Bit 3 0 0 0 Bit 2 Bit 1 Bit 0 TXF_RST RXF_RST EN_FIFO TXF_RST RXF_RST EN_FIFO 0 0 0
Legacy IR: This register is used to control FIFO functions of the IR. Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if the interrupt active level is set as 4 bytes and there are more than 4 data characters in the receiver FIFO, the interrupt will be activated to notify CPU to read the data from FIFO. TABLE: FIFO TRIGGER LEVEL BIT 7 0 0 1 1 Bit 4, 5: Reserved Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if UFR bit 0 = 1. Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to its initial state. This bit will be cleared to logical 0 by itself after being set to logical 1. Bit 1: Setting this bit to logical 1 resets the RX FIFO counter logic to its initial state. This bit will be cleared to a logical 0 by itself after being set to logical 1. Bit 0: This bit enables the 16550 (FIFO) mode of the IR. This bit should be set to logical 1 before other bits of UFR can be programmed. BIT 6 0 1 0 1 RX FIFO INTERRUPT ACTIVE LEVEL (BYTES) 01 04 08 14
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Advanced IR: Bit 7, 6: RXFTL1, 0 - Receiver FIFO Threshold Level Its definition is the same as Legacy IR. RXTH_I becomes 1 when the Receiver FIFO Threshold Level is equal or larger than the defined value shown as follow. RXFTL1, 0 (Bit 7, 6) 00 01 10 11 RX FIFO Threshold Level (FIFO Size: 16-byte) 1 4 8 14 RX FIFO Threshold Level (FIFO Size: 32-byte) 1 4 16 26
Bit 5, 4:
Note that the FIFO Size is selectable in SET2.Reg4. TXFTL1, 0 - Transmitter FIFO Threshold Level TXTH_I (Transmitter Threshold Level Interrupt) is set to 1 when the Transmitter Threshold Level is less than the programmed value shown as follows. TXFTL1, 0 (Bit 5, 4) 00 01 10 11 TX FIFO Threshold Level (FIFO Size: 16-byte) 1 3 9 13 TX FIFO Threshold Level (FIFO Size: 32-byte) 1 7 17 25
Bit 3 ~0
Same as in Legacy IR Mode
4.2.4 Set0.Reg3 - IR Control Register/Set Select Register (UCR/SSR): These two registers share the same address. In all Register Sets, Set Select Register (SSR) can be programmed to select a desired Set but IR Control Register can only be programmed in Set 0 and Set 1. In other words, writing to Reg3 in Sets other than Set 0 and Set 1 will not affect IR Control Register. The mapping of entry Set and programming value is shown as follows. SSR Bits 3 2
N N
7 0 1 1 1 1 1 1 1
6
N
5
N
4
N
1
N
0
N
Hex Value

Selected Set Set 0 Set1 Set 2 Set 3 Set 4 Set 5 Set 6 Set 7
1 1 1 1 1 1
Any combination except those used in SET 2~7 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0
0xE0 0xE4 0xE8 0xEC 0xF0 0xF4
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W83977F/ W83977AF
PRELIMINARY
4.2.5 Set0.Reg4 - Handshake Control Register (HCR) Mode B7 B6 B5 B4 Legacy IR 0 0 0 XLOOP Advanced IR AD_MD2 AD_MD1 AD_MD0 SIR_PLS Reset Value 0 1 1 0 B3 EN_IRQ TX_WT 0 B2 0 EN_DMA 0 B1 0 0 0 B0 0 0 0
Legacy IR Register: This register controls the pins of IR used for handshaking with peripherals such as modem, and controls the diagnostic mode of IR. Bit 4: When this bit is set to logical 1, the legacy IR enters diagnostic mode by an internal loopback: IRTX is forced to logical 0, and IRRX is isolated from the communication link instead of the TSR. Bit 3: The legacy IR interrupt output is enabled by setting this bit to logic 1. Advanced IR Register: Bit 7~5 Advanced SIR/ASK-IR, MIR, FIR, Remote Controller Modes: AD_MD2~0 - Advanced IR/Infrared Mode Select. These registers are active when Advanced IR Select (ADV_SL, in Set2.Reg2.Bit0) is set to 1. Operational mode selection is defined as follows. When backward operation occurs, these registers will be reset to 0 and fall back to legacy IR mode. AD_MD2~0 (Bit 7, 6, 5) 000 001 010 011 100 101 110 111 Bit 4: Selected Mode Reserved Low speed MIR (0.576M bps) Advanced ASK-IR Advanced SIR High Speed MIR (1.152M bps) FIR (4M bps) Consumer IR Reserved
Bit 3:
MIR, FIR Modes: SIR_PLS - Send Infrared Pulse Writing 1 to this bit will send a 2 s long infrared pulse after physical frame end. This is to signal to SIR that the high speed infrared is still in. This bit will be auto cleared by hardware. Other Modes: Not used. MIR, FIR modes: TX_WT - Transmission Waiting If this bit is set to 1, the transmitter will wait for TX FIFO reaching threshold level or transmitter time-out before it begins to transmit data which prevents short queues of data bytes from transmitting prematurely. This is to avoid Underrun. Other Modes: Not used.
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Publication Release Date: March 1998 Revision 0.58
W83977F/ W83977AF
PRELIMINARY
MIR, FIR modes: EN_DMA - Enable DMA Enable DMA function for transmitting or receiving. Before using this, the DMA channel should be selected first. If only RX DMA channel is set and TX DMA channel is disabled, then the single DMA channel is used. In the single channel system, the bit of D_CHSW (DMA channel swap, in Set 2.Reg2.Bit3) will determine if it is RX_DMA or TX_DMA channel. Other modes: Not used. Bit 1, 0: RTS, DTR Functional definitions is the same as in legacy IR mode. Bit 2:
4.2.6 Set0.Reg5 - IR Status Register (USR) Mode B7 Legacy IR RFEI Advanced IR LB_INFR Reset Value 0 B6 TSRE TSRE 0 B5 TBRE TBRE 0 B4 B3 B2 SBD NSER PBER MX_LEX PHY_ERR CRC_ERR 0 0 0 B1 OER OER 0 B0 RDR RDR 0
Legacy IR Register: These registers are defined the same as previous description. Advanced IR Register: Bit 7: MIR, FIR Modes: LB_INFR - Last Byte In Frame End Set to 1 when last byte of a frame is in the bottom of FIFO. This bit separates one frame from another when RX FIFO has more than one frame. Bit 6, 5: Same as legacy IR description. Bit 4: MIR, FIR modes: MX_LEX - Maximum Frame Length Exceed Set to 1 when the length of a frame from the receiver has exceeded the programmed frame length defined in SET4.Reg6 and Reg5. If this bit is set to 1, the receiver will not receive any data to RX FIFO. Bit 3: MIR, FIR modes: PHY_ERR - Physical Layer Error Set to 1 when an illegal data symbol is received. The illegal data symbol is defined in physical layer of IrDA version 1.1. When this bit is set to 1, the decoder of receiver will be aborted and a frame end signal is set to 1. Bit 2: MIR, FIR Modes: CRC_ERR - CRC Error Set to 1 when an attached CRC is erroneous. Bit 1, 0: OER - Overrun Error, RDR - RBR Data Ready Definitions are the same as legacy IR. 4.2.7 Set0.Reg6 - Reserved 4.2.8 Set0.Reg7 - User Defined Register (UDR/AUDR) Mode Bit 7 Legacy IR Bit 7 Advanced FLC_ACT IR Reset Value 0 Bit 6 Bit 6 UNDRN 0 Bit 5 Bit 5 RX_BSY/ RX_IP 0 Bit 4 Bit 4 LST_FE/ RX_PD 0 Bit 3 Bit 3 S_FEND 0 Bit 2 Bit 2 0 0 Bit 1 Bit 1 LB_SF 0 Bit 0 Bit 0 RX_TO 0
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Publication Release Date: March 1998 Revision 0.58
W83977F/ W83977AF
PRELIMINARY
Legacy IR Register: This is a temporary register that can be accessed and defined by the user. Advanced IR Register: Bit 7 MIR, FIR Modes: FLC_ACT - Flow Control Active Set to 1 when the flow control occurs. Cleared to 0 when this register is read. Note that this will be affected by Set5.Reg2 which controls the SIR mode switches to MIR/FIR mode or MIR/FIR mode operated in DMA function switches to SIR mode. Bit 6 MIR, FIR Modes: UNDRN - Underrun Set to 1 when transmitter is empty and S_FEND (bit 3 of this register) is not set in PIO mode or no TC (Terminal Count) in DMA mode. Cleared to 0 after a write to 1. Bit 5 MIR, FIR Modes: RX_BSY - Receiver Busy Set to 1 when receiver is busy or active in process. Remote IR mode: RX_IP - Receiver in Process Set to 1 when receiver is in process. Bit 4: MIR, FIR modes: LST_FE - Lost Frame End Set to 1 when a frame end in a entire frame is lost. Cleared to 0 when this register is read. Remote IR Modes: RX_PD - Receiver Pulse Detected Set to 1 when one or more remote pulses are detected. Cleared to 0 when this register is read. Bit 3 MIR, FIR Modes: S_FEND - Set a Frame End Set to 1 when trying to terminate the frame, that is, the procedure of PIO command is An Entire Frame = Write Frame Data (First) + Write S_FEND (Last) This bit should be set to 1, if use in PIO mode, to avoid transmitter underrun. Note that setting S_FEND to 1 is equivalent to TC (Terminal Count) in DMA mode. Therefore, this bit should be set to 0 in DMA mode. Bit 2: Reserved. Bit 1: MIR, FIR Modes: LB_SF - Last Byte Stay in FIFO A 1 in this bit indicates one or more frame ends still stay in receiver FIFO. Bit 0: MIR, FIR, Remote IR Modes: RX_TO - Receiver FIFO or Frame Status FIFO time-out Set to 1 when receiver FIFO or frame status FIFO time-out occurs
4.3 Set1 - Legacy Baud Rate Divisor Register
Address Offset 0 1 2 3 4 5 6 7 Register Name BLL BHL ISR/UFR UCR/SSR HCR USR HSR UDR/ESCR Register Description Baud Rate Divisor Latch (Low Byte) Baud Rate Divisor Latch (High Byte) Interrupt Status or IR FIFO Control Register IR Control or Sets Select Register Handshake Control Register IR Status Register Handshake Status Register User Defined Register - 60 Publication Release Date: March 1998 Revision 0.58
W83977F/ W83977AF
PRELIMINARY
4.3.1 Set1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) These two registers of BLL and BHL are baud rate divisor latch in the legacy SIR/ASK-IR mode. Accessing these registers in Advanced IR mode will cause backward operation, that is, UART will fall back to legacy SIR mode and clear some register values as shown in the following table. Set & Register Set 0.Reg 4 Set 2.Reg 2 Set 4.Reg 3 Advanced Mode DIS_BACK=N Bit 7~5 Bit 0, 5, 7 Bit 2, 3 Legacy Mode DIS_BACK=0 Bit 5, 7 -
Note that DIS_BACK=1 (Disable Backward operation) in legacy SIR/ASK-IR mode will not affect any register which is meaningful in legacy SIR/ASK-IR. 4.3.2 Set1.Reg 2~7 These registers are defined as the same as Set 0 registers.
4.4 Set2 - Interrupt Status or IR FIFO Control Register (ISR/UFR)
These registers are only used in advanced modes. Address Offset Register Name Register Description Advanced Baud Rate Divisor Latch (Low Byte) 0 ABLL Advanced Baud Rate Divisor Latch (High Byte) 1 ABHL Advanced IR Control Register 1 2 ADCR1 Sets Select Register 3 SSR Advanced IR Control Register 2 4 ADCR2 5 Reserved Transmitter FIFO Depth 6 TXFDTH Receiver FIFO Depth 7 RXFDTH 4.4.1 Reg0, 1 - Advanced Baud Rate Divisor Latch (ABLL/ABHL) These two registers are the same as legacy IR baud rate divisor latch in SET 1.Reg0~1. In advanced SIR/ASK-IR mode, user should program these registers to set baud rate. This is to prevent backward operation from occurring. 4.4.2 Reg2 - Advanced IR Control Register 1 (ADCR1) Bit 6 0 Bit 5 EN_LOUT 0 Bit 4 Bit 3 Bit 2 ALOOP D_CHSW DMATHL 0 0 0 Bit 1 DMA_F 0 Bit 0 ADV_SL 0
Mode Bit 7 Advanced IR BR_OUT Reset Value 0 Bit 7:
Bit 6: Bit 5:
BR_OUT - Baud Rate Clock Output When written to 1, the programmed baud rate clock will be output to DTR pin. This bit is only used to test baud rate divisor. Reserved, write 0. EN_LOUT - Enable Loopback Output A write to 1 will enable transmitter to output data to IRTX pin when loopback operation. Internal data can be verified through an output pin by setting this bit.
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W83977F/ W83977AF
PRELIMINARY
Bit 4: Bit 3: ALOOP - All Mode Loopback A write to 1 will enable loopback in all modes. D_CHSW - DMA TX/RX Channel Swap If only one DMA channel operates in MIR/FIR mode, then the DMA channel can be swapped. D_CHSW DMA Channel Selected 0 Receiver (Default) 1 Transmitter A write to 1 will enable output data when ALOOP=1. DMATHL - DMA Threshold Level Set DMA threshold level as shown in the following table. DMATHL 0 1 Bit 1: TX FIFO Threshold 16-Byte 32-Byte 13 13 23 7 RX FIFO Threshold (16/32-Byte) 4 10
Bit 2:
Bit 0:
DMA_F - DMA Fairness DMA_F Function Description 0 DMA request (DREQ) is forced inactive after 10.5us 1 No effect DMA request. ADV_SL - Advanced Mode Select A write to 1 selects advanced mode.
4.4.3 Reg3 - Sets Select Register (SSR) Reading this register returns E0H. Writing a value selects Register Set. Reg. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 SSR SSR7 SSR6 SSR5 SSR4 SSR3 SSR2 Refault Value 1 1 1 0 0 0 4.4.4 Reg4 - Advanced IR Control Register 2 (ADCR2) Mode Bit 7 Advanced IR DIS_BACK Reset Value 0 Bit 7: Bit 6 0
Bit 1 SRR1 0
Bit 0 SRR0 0
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PR_DIV1 PR_DIV0 RX_FSZ1 RX_FSZ0 TX_FSZ1 TXFSZ0 0 0 0 0 0 0
Bit 6: Bit 5, 4:
DIS_BACK - Disable Backward Operation A write to 1 disables backward legacy IR mode. When operate in legacy SIR/ASK-IR mode, this bit should be set to 1 to avoid backward operation. Reserved, write 0. PR_DIV1~0 - Pre-Divisor 1~0. These bits select pre-divisor for external input clock 24M Hz. The clock goes through the pre-divisor then input to baud rate divisor of IR. PR_DIV1~0 00 01 10 11 Pre-divisor 13.0 1.625 6.5 1 Max. Baud Rate 115.2K bps 921.6K bps 230.4K bps 1.5M bps Publication Release Date: March 1998 Revision 0.58
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W83977F/ W83977AF
PRELIMINARY
Bit 3, 2: RX_FSZ1~0 - Receiver FIFO Size 1~0 These bits setup receiver FIFO size when FIFO is enable. RX_FSZ1~0 00 01 1X Bit 1, 0: RX FIFO Size 16-Byte 32-Byte Reserved
TX_FSZ1~0 - Transmitter FIFO Size 1~0 These bits setup transmitter FIFO size when FIFO is enable. TX_FSZ1~0 00 01 1X TX FIFO Size 16-Byte 32-Byte Reserved
TABLE: SIR Baud Rate BAUD RATE FROM DIFFERENT PRE-DIVIDER Pre-Div: 13 1.8461M Hz 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 Pre-Div:1.625 14.769M Hz 400 600 880 1076 1200 2400 4800 9600 14400 16000 19200 28800 38400 57600 76800 153600 307200 460800 921600 Pre-Div: 1.0 24M Hz 650 975 1430 1478.5 1950 3900 7800 15600 23400 26000 31200 46800 62400 93600 124800 249600 499200 748800 1497600 Decimal divisor used to generate 16X clock 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 1 Error Percentage between desired and actual ** ** 0.18% 0.099% ** ** ** ** ** 0.53% ** ** ** ** ** ** ** ** **
** The percentage error for all baud rates, except where indicated otherwise, is 0.16%.
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Publication Release Date: March 1998 Revision 0.58
W83977F/ W83977AF
PRELIMINARY
4.4.5 Reg6 - Transmitter FIFO Depth (TXFDTH) (Read Only) Mode Advanced IR
Reset Value
Bit 7 0 0
Bit 6 0 0
Bit 5 TXFD5 0
Bit 4 TXFD4 0
Bit 3 TXFD3 0
Bit 2 TXFD2 0
Bit 1 TXFD1 0
Bit 0 TXFD1 0
Bit 7~6: Bit 5~0:
Reserved, Read 0. Reading these bits returns the current transmitter FIFO depth, that is, the number of bytes left in the transmitter FIFO.
4.4.6 Reg7 - Receiver FIFO Depth (RXFDTH) (Read Only) Mode Advanced IR
Reset Value
Bit 7 0 0
Bit 6 0 0
Bit 5 RXFD5 0
Bit 4 RXFD4 0
Bit 3 RXFD3 0
Bit 2 RXFD2 0
Bit 1 RXFD1 0
Bit 0 RXFD1 0
Bit 7~6: Bit 5~0:
Reserved, Read 0. Reading these bits returns the current receiver FIFO depth, that is, the number of bytes left in the receiver FIFO.
4.5 Set3 - Version ID and Mapped Control Registers
Address Offset 0 1 2 3 4 5 6 7 Register Name AUID MP_UCR MP_UFR SSR Reversed Reserved Reserved Reserved Register Description Advanced IR ID Mapped IR Control Register Mapped IR FIFO Control Register Sets Select Register -
4.5.1 Reg0 - Advanced IR ID (AUID) This register is read only. It stores advanced IR version ID. Reading it returns 1XH. Reg. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 SSR SSR7 SSR6 SSR5 SSR4 SSR3 SSR2 SRR1 Default Value 0 0 0 1 X X X
Bit 0 SRR0 X
4.5.2 Reg1 - Mapped IR Control Register (MP_UCR) This register is read only. Reading this register returns IR Control Register value of Set 0. Reg. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 SSR SSR7 SSR6 SSR5 SSR4 SSR3 SSR2 SRR1 Default Value 0 0 0 0 0 0 0
Bit 0 SRR0 0
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Publication Release Date: March 1998 Revision 0.58
W83977F/ W83977AF
PRELIMINARY
4.5.3 Reg2 - Mapped IR FIFO Control Register (MP_UFR) This register is read only. Reading this register returns IR FIFO Control Register (UFR) value of SET 0. Reg. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSR SSR7 SSR6 SSR5 SSR4 SSR3 SSR2 SRR1 SRR0 Default Value 0 0 0 0 0 0 0 0 4.5.4 Reg3 - Sets Select Register (SSR) Reading this register returns E4H. Writing a value selects a Register Set. Reg. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 SSR SSR7 SSR6 SSR5 SSR4 SSR3 SSR2 Default Value 1 1 1 0 0 1
Bit 1 SRR1 0
Bit 0 SRR0 0
4.6 Set4 - TX/RX/Timer counter registers and IR control registers.
Address Offset 0 1 2 3 4 5 6 7 Register Name TMRL TMRH IR_MSL SSR TFRLL TFRLH RFRLL RFRLH Register Description Timer Value Low Byte Timer Value High Byte Infrared Mode Select Sets Select Register Transmitter Frame Length Low Byte Transmitter Frame Length High Byte Receiver Frame Length Low Byte Receiver Frame Length High Byte
4.6.1 Set4.Reg0, 1 - Timer Value Register (TMRL/TMRH) This is a 12-bit timer whose resolution is 1ms, that is, the maximum programmable time is 212-1 ms. The timer is a down-counter and starts counting down when EN_TMR (Enable Timer) of Set4.Reg2 is set to 1. When the timer counts down to zero and EN_TMR=1, the TMR_I is set to 1 and a new initial value will be loaded into counter. 4.6.2 Set4.Reg2 - Infrared Mode Select (IR_MSL) Mode Advanced IR
Reset Value
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 IR_MSL1 0
Bit 2 IR_MSL0 0
Bit 1 TMR_TST 0
Bit 0 EN_TMR 0
Bit 7~4: Reserved, write to 0. Bit 3, 2: IR_MSL1, 0 - Infrared Mode Select Select legacy IR, SIR, or ASK-IR mode. Note that in legacy SIR/ASK-IR user should set DIS_BACK=1 to avoid backward when programming baud rate. IR_MSL1, 0 00 01 10 11 Operation Mode Selected Legacy IR CIR Legacy ASK-IR Legacy SIR
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W83977F/ W83977AF
PRELIMINARY
Bit 1: TMR_TST - Timer Test When set to 1, reading the TMRL/TMRH returns the programmed values of TMRL/TMRH instead of the value of down counter. This bit is for testing timer register. EN_TMR - Enable Timer A write to 1 will enable the timer.
Bit 0:
4.6.3 Set4.Reg3 - Set Select Register (SSR) Reading this register returns E8H. Writing this register selects Register Set. Reg. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 SSR SSR7 SSR6 SSR5 SSR4 SSR3 SSR2 Default Value 1 1 1 1 1 0
Bit 1 SRR1 0
Bit 0 SRR0 0
4.6.4 Set4.Reg4, 5 - Transmitter Frame Length (TFRLL/TFRLH) Reg. TFRLL
Reset Value
TFRLH
Reset Value
Bit 7 bit 7 0 -
Bit 6 bit 6 0 -
Bit 5 bit 5 0 -
Bit 4 bit 4 0 bit 12 0
Bit 3 bit3 0 bit 11 0
Bit 2 bit 2 0 bit 10 0
Bit 1 bit 1 0 bit 9 0
Bit 0 bit 0 0 bit 8 0
These are combined to be a 13-bit register. Writing these registers programs the transmitter frame length of a package. These registers are only valid when APM=1 (automatic package mode, Set5.Reg4.bit5). When APM=1, the physical layer will split data stream to a programmed frame length if the transmitted data is larger than the programmed frame length. When these registers are read, they will return the number of bytes which is not transmitted from a frame length programmed. 4.6.5 Set4.Reg6, 7 - Receiver Frame Length (RFRLL/RFRLH) Reg. RFRLL
Reset Value
RFRLH
Reset Value
Bit 7 bit 7 0 -
Bit 6 bit 6 0 -
Bit 5 bit 5 0 -
Bit 4 bit 4 0 bit 12 0
Bit 3 bit 3 0 bit 11 0
Bit 2 bit 2 0 bit 10 0
Bit 1 bit 1 0 bit 9 0
Bit 0 bit 0 0 bit 8 0
These are combined to be a 13-bit registers and up counter. The length of receiver frame will be limited to the programmed frame length. If the received frame length is larger than the programmed receiver frame length, the bit of MX_LEX (Maximum Length Exceed) will be set to 1. Simultaneously, the receiver will not receive any more data to RX FIFO until the next start flag of the next frame, which is defined in the physical layer IrDA 1.1. Reading these registers returns the number of received data bytes of a frame from the receiver.
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Publication Release Date: March 1998 Revision 0.58
W83977F/ W83977AF
PRELIMINARY 4.7 Set 5 - Flow control and IR control and Frame Status FIFO registers
Address Offset 0 1 2 3 4 5 6 7 Register Name FCBLL FCBHL FC_MD SSR IRCFG1 FS_FO RFRLFL RFRLFH Register Description Flow Control Baud Rate Divisor Latch Register (Low Byte) Flow Control Baud Rate Divisor Latch Register (High Byte) Flow Control Mode Operation Sets Select Register Infrared Configure Register Frame Status FIFO Register Receiver Frame Length FIFO Low Byte Receiver Frame Length FIFO High Byte
4.7.1 Set5.Reg0, 1 - Flow Control Baud Rate Divisor Latch Register (FCDLL/ FCDHL) If flow control is enforced when UART switches mode from MIR/FIR to SIR, then the pre-programmed baud rate of FCBLL/FCBHL are loaded into advanced baud rate divisor latch (ADBLL/ADBHL). 4.7.2 Set5.Reg2 - Flow Control Mode Operation (FC_MD) These registers control flow control mode operation as shown in the following table. Reg. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 FC_MD FC_MD2 FC_MD1 FC_MD0 FC_DSW EN_FD EN_BRFC Reset Value 0 0 0 0 0 0 0 Bit 7~5
Bit 0 EN_FC 0
Bit 4: Bit 3:
FC_MD2 - Flow Control Mode When flow control is enforced, these bits will be loaded into AD_MD2~0 of advanced HSR (Handshake Status Register). These three bits are defined as same as AD_MD2~0. Reserved, write 0. FC_DSW - Flow Control DMA Channel Swap A write to 1 allow user to swap DMA channel for transmitter or receiver when flow control is enforced. FC_DSW 0 1 Next Mode After Flow Control Occurred Receiver Channel Transmitter Channel
Bit 2: Bit 1:
Bit 0:
EN_FD - Enable Flow DMA Control A write to 1 enables UART to use DMA channel when flow control is enforced. EN_BRFC - Enable Baud Rate Flow Control A write to 1 enables FC_BLL/FC_BHL (Flow Control Baud Rate Divider Latch, in Set5.Reg1~0) to be loaded into advanced baud rate divisor latch (ADBLL/ADBHL, in Set2.Reg1~0). EN_FC - Enable Flow Control A write to 1 enables flow control function and bit 7~1 of this register.
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Publication Release Date: March 1998 Revision 0.58
W83977F/ W83977AF
PRELIMINARY
4.7.3 Set5.Reg3 - Sets Select Register (SSR) Writing this register selects Register Set. Reading this register returns ECH. Reg. SSR
Default Value
Bit 7 SSR7 1
Bit 6 SSR6 1
Bit 5 SSR5 1
Bit 4 SSR4 0
Bit 3 SSR3 1
Bit 2 SSR2 1
Bit 1 SRR1 0
Bit 0 SRR0 0
4.7.4 Set5.Reg4 - Infrared Configure Register 1 (IRCFG1) Reg. IRCFG1
Reset Value
Bit 7 0
Bit 6 FSF_TH 0
Bit 5 FEND_M 0
Bit 4 AUX_RX 0
Bit 3 0
Bit 2 0
Bit 1 IRHSSL 0
Bit 0 IR_FULL 0
Bit 7: Bit 6:
Reserved, write 0. FSF_TH - Frame Status FIFO Threshold Set this bit to determine the frame status FIFO threshold level and to generate the FSF_I. The threshold level values are defined as follows. FSF_TH 0 1 Status FIFO Threshold Level 2 4
Bit 5:
Bit 4: Bit 3~2: Bit 1:
Bit 0:
FEND_MD - Frame End Mode A write to 1 enables hardware to split data stream into equal length frame automatically as defined in Set4.Reg4 and Set4.Reg5, i.e., TFRLL/TFRLH. AUX_RX - Auxiliary Receiver Pin A write to 1 selects IRRX input pin. (Refer to Set7.Reg7.Bit5) Reserved, write 0. IRHSSL - Infrared Handshake Status Select When set to 0, the HSR (Handshake Status Register) operates as same as defined in IR mode. A write to 1 will disable HSR, and reading HSR returns 30H. IR_FULL - Infrared Full Duplex Operation When set to 0, IR module operates in half duplex. A write to 1 makes IR module operate in full duplex.
4.7.5Set5.Reg5 - Frame Status FIFO Register (FS_FO) This register shows the bottom byte of frame status FIFO. Reg. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 FS_FO FSFDR LST_FR MX_LEX PHY_ERR CRC_ERR RX_OV Reset Value 0 0 0 0 0 0 0 Bit 7: Bit 6: Bit 5: FSFDR - Frame Status FIFO Data Ready Indicate that a data byte is valid in frame status FIFO bottom. LST_FR - Lost Frame Set to 1 when one or more frames have been lost. Reserved.
Bit 0 FSF_OV 0
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Publication Release Date: March 1998 Revision 0.58
W83977F/ W83977AF
PRELIMINARY
Bit 4: MX_LEX - Maximum Frame Length Exceed Set to 1 when incoming data exceeds programmed maximum frame length defined in Set4.Reg6 and Set4.Reg7. This bit is in frame status FIFO bottom and is valid only when FSFDR=1 (Frame Status FIFO Data Ready). PHY_ERR - Physical Error When receiving data, any physical layer error as defined in IrDA 1.1 will set this bit to 1. This bit is in frame status FIFO bottom and is valid only when FSFDR=1 (Frame Status FIFO Data Ready). CRC_ERR - CRC Error Set to 1 when receive a bad CRC in a frame. This CRC belongs to physical layer as defined in IrDA 1.1. This bit is in frame status FIFO bottom and is valid only when FSFDR=1 (Frame Status FIFO Data Ready). RX_OV - Received Data Overrun Set to 1 when receiver FIFO overruns. FSF_OV - Frame Status FIFO Overrun Set to 1 When frame status FIFO overruns.
Bit 3:
Bit 2:
Bit 1: Bit 0:
4.7.6 Set5.Reg6, 7 - Receiver Frame Length FIFO (RFLFL/RFLFH) or Lost Frame Number (LST_NU) Reg. RFLFL/ LST_NU
Reset Value
RFLFH
Reset Value
Bit 7 Bit 7 0 0
Bit 6 Bit 6 0 0
Bit 5 Bit 5 0 0
Bit 4 Bit 4 0 Bit 12 0
Bit 3 Bit 3 0 Bit 11 0
Bit 2 Bit 2 0 Bit 10 0
Bit 1 Bit 1 0 Bit 9 0
Bit 0 Bit 0 0 Bit 8 0
Receiver Frame Length FIFO (RFLFL/RFLFH): These are combined to be a 13-bit register. Reading these registers returns received byte count for the frame. When read, the register of RFLFH will pop-up another frame status and frame length if FSFDR=1 (Set5.Reg4.Bit7). Lost Frame Number (LST_NU): When LST_FR=1 (Set5.Reg4.Bit6), Reg6 stands for LST_NU which is a 8-bit register holding the number of frames lost in succession.
4.8 Set6 - IR Physical Layer Control Registers
Address Offset 0 1 2 3 4 5 6 7 Register Name IR_CFG2 MIR_PW SIR_PW SSR HIR_FNU Reserved Reserved Reserved Register Description Infrared Configure Register 2 MIR (1.152M bps or 0.576M bps) Pulse Width SIR Pulse Width Sets Select Register High Speed Infrared Flag Number -
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Publication Release Date: March 1998 Revision 0.58
W83977F/ W83977AF
PRELIMINARY
4.8.1 Set6.Reg0 - Infrared Configure Register 2 (IR_CFG2) This register controls ASK-IR, MIR, FIR operations. Reg.
Reset Value
Bit 7 0
Bit 6 0
Bit 5 1
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 0
Bit 0 0
IR_CFG2 SHMD_N SHDM_N FIR_CRC MIR_CRC
INV_CRC DIS_CRC
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 2: Bit 1: Bit 0:
SHMD_N - ASK-IR Modulation Disable SHMD_N Modulation Mode 0 IRTX modulate 500K Hz Square Wave 1 Re-rout IRTX SHDM_N - ASK-IR Demodulation Disable SHDM_N Demodulation Mode 0 Demodulation 500K Hz 1 Re-rout IRRX FIR_CRC - FIR (4M bps) CRC Type FIR_CRC CRC Type 0 16-bit CRC 1 32-bit CRC Note that the 16/32-bit CRC are defined in IrDA 1.1 physical layer. MIR_CRC - MIR (1.152M/0.576M bps) CRC Type MIR_CRC CRC Type 0 16-bit CRC 1 32-bit CRC INV_CRC - Inverting CRC When set to 1, the CRC is inversely output in physical layer. DIS_CRC - Disable CRC When set to 1, the transmitter does not transmit CRC in physical layer. Reserved, write 1.
4.8.2 Set6.Reg1 - MIR (1.152M/0.576M bps) Pulse Width Bit 7 Bit 6 Bit 5 Bit 4 M_PW4 Reset Value 0 0 0 0 This 5-bit register sets MIR output pulse width. M_PW4~0 00000 00001 00010
...
Reg. MIR_PW
Bit 3 M_PW3 1
Bit 2 M_PW2 0
Bit 1 M_PW1 1
Bit 0 M_PW0 0
MIR Pulse Width (1.152M bps) 0 ns 20.83 ns 41.66 (==20.83*2) ns
...
MIR Output Width (0.576M bps) 0 ns 41.66 ns 83.32 (==41.66*2) ns
...
k10
...
20.83*k10 ns
...
41.66*k10 ns
...
11111
645 ns
1290 ns
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Publication Release Date: March 1998 Revision 0.58
W83977F/ W83977AF
PRELIMINARY
4.8.3 Set6.Reg2 - SIR Pulse Width Reg. SIR_PW
Reset Value
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 S_PW4 0
Bit 3 S_PW3 0
Bit 2 S_PW2 0
Bit 1 S_PW1 0
Bit 0 S_PW0 0
This 5-bit register sets SIR output pulse width. S_PW4~0 00000 01101 Others SIR Output Pulse Width 3/16 bit time of IR 1.6 us 1.6 us
4.8.4 Set6.Reg3 - Set Select Register Select Register Set by writing a set number to this register. Reading this register returns F0H. Reg. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSR SSR7 SSR6 SSR5 SSR4 SSR3 SSR2 SRR1 SRR0 Default Value 1 1 1 1 0 0 0 0 4.8.5 Set6.Reg4 - High Speed Infrared Beginning Flag Number (HIR_FNU) Reg. HIR_FNU
Reset Value
Bit 7 M_FG3 0
Bit 6 M_FG2 0
Bit 5 M_FG1 1
Bit 4 M_FG0 0
Bit 3 F_FL3 1
Bit 2 F_FL2 0
Bit 1 F_FL1 1
Bit 0 F_FL0 0
Bit 7~4:
M_FG3~0 - MIR beginning Flag Number These bits define the number of transmitter Start Flag of MIR. Note that the number of MIR start flag should be equal or more than two which is defined in IrDA 1.1 physical layer. The default value is 2. Beginning Flag Number Reserved 1 2 (Default) 3 4 5 6 8 M_FG3~0 1000 1001 1010 1011 1100 1101 1110 1111 Beginning Flag Number 10 12 16 20 24 28 32 Reserved
M_FG3~0 0000 0001 0010 0011 0100 0101 0110 0111
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PRELIMINARY
Bit 3~0: F_FG3~0 - FIR Beginning Flag Number These bits define the number of transmitter Preamble Flag in FIR. Note that the number of FIR start flag should be equal to sixteen which is defined in IrDA 1.1 physical layer. The default value is 16. Beginning Flag Number Reserved 1 2 3 4 5 6 8 M_FG3~0 1000 1001 1010 1011 1100 1101 1110 1111 Beginning Flag Number 10 12 16 (Default) 20 24 28 32 Reserved
M_FG3~0 0000 0001 0010 0011 0100 0101 0110 0111
4.9 Set7 - Remote control and IR module selection registers
Address Offset 0 1 2 3 4 5 6 7 Register Name RIR_RXC RIR_TXC RIR_CFG SSR IRM_SL1 IRM_SL2 IRM_SL3 IRM_CR Register Description Remote Infrared Receiver Control Remote Infrared Transmitter Control Remote Infrared Config Register Sets Select Register Infrared Module (Front End) Select 1 Infrared Module Select 2 Infrared Module Select 3 Infrared Module Control Register
4.9.1 Set7.Reg0 - Remote Infrared Receiver Control (RIR_RXC) Reg. RIR_RXC
Default Value
Bit 7 RX_FR2 0
Bit 6 RX_FR1 0
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RX_FR0 RX_FSL4 RX_FSL3 RX_FSL2 RX_FSL1 RX_FSL0 1 0 1 0 0 1
This register defines frequency range of receiver of remote IR. Bit 7~5: RX_FR2~0 - Receiver Frequency Range 2~0. These bits select the input frequency range of the receiver. It is implemented through a band pass filter, i.e., only the input signals whose frequency lies in the range defined in this register will be received. Bit 4~0: RX_FSL4~0 - Receiver Frequency Select 4~0. Select the operation frequency of receiver.
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PRELIMINARY
Table: Low Frequency range select of receiver.
001 RX_FSL4~0 00010 00011 00100 00101 00110 00111 01000 01001 01011 01100 01101 01111 10000 10010 10011 10101 10111 11010 11011 11101 Min. 26.1 28.2 29.4 30.0 31.4 32.1 32.8 33.6* 34.4 36.2 37.2 38.2 40.3 41.5 42.8 44.1 45.5 48.7 50.4 54.3 Max. 29.6 32.0 33.3 34.0 35.6 36.4 37.2 38.1* 39.0 41.0 42.1 43.2 45.7 47.1 48.5 50.0 51.6 55.2 57.1 61.5 RX_FR2~0 (Low Frequency) 010 Min. Max. 24.7 26.7 27.8 28.4 29.6 30.3 31.0 31.7 32.5 34.2 35.1 36.0 38.1 39.2 40.4 41.7 43.0 46.0 47.6 51.3 31.7 34.3 35.7 36.5 38.1 39.0 39.8 40.8 41.8 44.0 45.1 46.3 49.0 50.4 51.9 53.6 55.3 59.1 61.2 65.9 011 Min. 23.4 25.3 26.3 26.9 28.1 28.7 29.4 30.1 30.8 32.4 33.2 34.1 36.1 37.2 38.3 39.5 40.7 43.6 45.1 48.6 Max. 34.2 36.9 38.4 39.3 41.0 42.0 42.9 44.0 45.0 47.3 48.6 49.9 52n.7 54.3 56.0 57.7 59.6 63.7 65.9 71.0
Note that those unassigned combinations are reserved.
Table: High Frequency range select of receiver RX_FR2~0 (High Frequency) 001 Min. Max. RX_FSL4~0 355.6 457.1 00011 380.1 489.8 01000 410.3 527.4 01011
Note that those unassigned combinations are reserved.
Table: SHARP ASK-IR receiver frequency range select.
RX_FR2~0 001 480.0* 533.3* RX_FSL4~0 (SHARP ASK-IR) 010 011 100 457.1 564.7 436.4 600.0 417.4 640.0 101 400.0 685.6 110 384.0 738.5
Note that those unassigned combinations are reserved.
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PRELIMINARY
4.9.2 Set7.Reg1 - Remote Infrared Transmitter Control (RIR_TXC) Reg. RIR_TXC
Default Value
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TX_PW2 TX_PW1 TX_PW0 TX_FSL4 TX_FSL3 TX_FSL2 TX_FSL1 TX_FSL0 0 1 1 0 1 0 0 1
This Register defines the transmitter frequency and pulse width of remote IR. Bit 7~5: TX_PW2~0 - Transmitter Pulse Width 2~ 0. Select the transmission pulse width. TX_PW2~0 010 011 100 101
Note that those unassigned combinations are reserved.
Low Frequency 6 s 7 s 9 s 10.6 s
High Frequency 0.7 s 0.8 s 0.9 s 1.0 s
Bit 4~0:
TX_FSL4~0 - Transmitter Frequency Select 4~0. Select the transmission frequency.
Table: Low frequency selected. TX_FSL4~0 00011 00100 ... 11101
Low Frequency 30K Hz 31K HZ ... 56K Hz
Note that those unassigned combinations are reserved.
Table: High frequency selected. TX_FSL4~0 00011 01000 01011
High Frequency 400K Hz 450K Hz 480K Hz
Note that those unassigned combinations are reserved.
4.9.3 Set7.Reg2 - Remote Infrared Config Register (RIR_CFG) Reg. RIR_CFG
Default Value
Bit 7 P_PNB 0
Bit 6 SMP_M 0
Bit 5 RXCFS 0
Bit 4 0
Bit 3 TX_CFS 0
Bit 2 RX_DM 0
Bit 1 Bit 0 TX_MM1 TX_MM0 0 0
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PRELIMINARY
Bit 7: P_PNB: Programming Pulse Number Coding. Write a 1 to select programming pulse number coding. The code format is defined as follows. (Number of bits) - 1
B7
B6
B5
B4
B3
B2
B1 B0
Bit value If the bit value is set to 0, the high pulse will be transmitted/received. If the bit value is set to 1, then no energy will be transmitted/received. SMP_M - Sampling Mode. To select receiver sampling mode. When set to 0 then uses T-period sampling, that the T-period is programmed IR baud rate. When set to 1, programmed baud rate will be used to do oversampling. RXCFS - Receiver Carry Frequency Select RXCFS Selected Frequency 30K ~ 56K Hz 0 400K ~ 480K Hz 1 Reserved, write 0. TX_CFS - Transmitter Carry Frequency Select. Select low speed or high speed transmitter carry frequency. TX_FCS Selected Frequency 30K ~ 56K Hz 0 400K ~ 480K Hz 1 RX_DM - Receiver Demodulation Mode. RX_DM Demodulation Mode Enable internal decoder 0 Disable internal decoder 1 TX_MM1~0 - Transmitter Modulation Mode 1~0 TX_MM1~0 TX Modulation Mode Continuously send pulse for logic 0 00 01 8 pulses for logic 0 and no pulse for logic 1. 10 6 pulses for logic 0 and no pulse for logic 1 Reserved. 11
Bit 6:
Bit 5:
Bit 4: Bit 3:
Bit 2:
Bit 1~0:
4.9.4 Set7.Reg3 - Sets Select Register (SSR) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Value 1 1 1 1 0 1 0 0 Reading this register returns F4H. Select Register Set by writing a set number to this register. Reg. SSR
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PRELIMINARY
4.9.5 Set7.Reg4 - Infrared Module (Front End) Select 1 (IRM_SL1) Reg. IRM_SL1
Default Value
Bit 7 Bit 6 Bit 5 Bit 4 IR_MSP SIR_SL2 SIR_SL1 SIR_SL0 0 0 0 0
Bit 3 0
Bit 2 Bit 1 Bit 0 AIR_SL2 AIR_SL1 AIR_SL0 0 0 0
Bit 7:
Bit 6~4:
Bit 3: Bit 2~0:
IR_MSP - IR Mode Select Pulse When set to 1, the transmitter (IRTX) will send a 64 s pulse to setup a special IR frontend operational mode. When IR front-end module uses mode select pin (MD) and transmitter IR pulse (IRTX) to switch between high speed IR (such as FIR or MIR) and low speed IR (SIR or ASK-IR), this bit should be used. SIR_SL2~0 - SIR (Serial IR) mode select. These bits are used to program the operational mode of the SIR front-end module. These values of SIR_SL2~0 will be automatically loaded to pins of IR_SL2~0, respectively, when (1) AM_FMT=1 (Automatic Format, in Set7.Reg7.Bit7); (2) the mode of Advanced IR is set to SIR (AD_MD2~0, in Set0.Reg4.Bit7~0). Reserved, write 0. AIR_SL2~0 - ASK-IR Mode Select. These bits setup the operational mode of ASK-IR front-end module when AM_FMT=1 and AD_MD2~0 are configured to ASK-IR mode. These values will be automatically loaded to IR_SL2~0, respectively.
4.9.6 Set7.Reg5 - Infrared Module (Front End) Select 2 (IRM_SL2) Reg. IRM_SL2
Default Value
Bit 7 0
Bit 6 Bit 5 Bit 4 FIR_SL2 FIR_SL1 FIR_SL0 0 0 0
Bit 3 0
Bit 2 Bit 1 Bit 0 MIR_SL2 MIR_SL1 MIR_SL0 0 0 0
Bit 7: Bit 6~4:
Bit 3: Bit 2~0:
Reserved, write 0. FIR_SL2~0 - FIR mode select. These bits setup the operational mode of FIR front-end module when AM_FMT=1 and AD_MD2~0 are configured to FIR mode. These values will be automatically loaded to IR_SL2~0, respectively. Reserved, write 0. MIR_SL2~0 - MIR Mode Select. These bits setup the MIR operational mode when AM_FMT=1 and AD_MD2~0 are configured to MIR mode. These values will be automatically loaded to IR_SL2~0, respectively.
4.9.7 Set7.Reg6 - Infrared Module (Front End) Select 3 (IRM_SL3) Reg. IRM_SL3
Default Value
Bit 7 0
Bit 6 Bit 5 Bit 4 LRC_SL2 LRC_SL1 LRC_SL0 0 0 0
Bit 3 0
Bit 2 Bit 1 Bit 0 HRC_SL2 HRC_SL1 HRC_SL0 0 0 0
Bit 7: Bit 6~4:
Reserved, write 0. LRC_SL2~0 - Low Speed Remote IR mode select. These bits setup the operational mode of low speed remote IR front-end module when AM_FMT=1 and AD_MD2~0 are configured to Remote IR mode. These values will be automatically loaded to IR_SL2~0, respectively.
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PRELIMINARY
Bit 3: Bit 2~0: Reserved, write 0. HRC_SL2~0 - High Speed Remote IR Mode Select. These bits setup the operational mode of high speed remote IR front-end module when AM_FMT=1 and .AD_MD2~0 are configured to Remote IR mode. These values will be automatically loaded to IR_SL2~0, respectively.
4.9.8 Set7.Reg7 - Infrared Module Control Register (IRM_CR) Reg. IRM_CR
Default Value
Bit 7 Bit 6 Bit 5 AM_FMT IRX_MSL IRSL0D 0 0 0
Bit 4 RXINV 0
Bit 3 TXINV 0
Bit 2 0
Bit 1 0
Bit 0 0
Bit 7:
Bit 6:
AM_FMT - Automatic Format A write to 1 will enable automatic format IR front-end module. These bit will affect the output of IR_SL2~0 which is referred by IR front-end module selection (Set7.Reg4~6) IRX_MSL - IR Receiver Module Select Select the receiver input path from the IR front end module if IR module has the separated high speed and low speed receiver path. If the IR module has only one receiving path, then this bit should be set to 0. IRX_MSL Receiver Pin selected IRRX (Low/High Speed) 0 IRRXH (High Speed) 1 IRSL0D - Direction of IRSL0 Pin Select function for IRRXH or IRSL0 because they share common pin and have different input/output direction. IRSL0_D Function IRRXH (I/P) 0 IRSL0 (O/P) 1
Bit 5:
Table: IR receiver input pin selection IRSL0D IRX_MSL 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1
AUX_RX 0 1 X X 0 1 X X
High Speed IR X X 0 1 X X 0 1
Selected IR Pin IRRX IRRXH IRRX IRRXH IRRX Reserved IRRX Reserved
Note: that (1) AUX_RX is defined in Set5.Reg4.Bit4, (2) high speed IR includes MIR (1.152M or 0.576M bps) and FIR (4M bps), (3) IRRX is the input of the low speed or high speed IR receiver, IRRXH is the input of the high speed IR receiver.
Bit 4: Bit 3: Bit 2~0:
RXINV - Receiving Signal Invert A write to 1 will Invert the receiving signal. TXINV - Transmitting Signal Invert A write to 1 will Invert the transmitting signal. Reserved, write 0.
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PRELIMINARY
5. PARALLEL PORT
5.1 Printer Interface Logic
The parallel port of the W83977F/ AF makes possible the attachment of various devices that accept eight bits of parallel data at standard TTL level. The W83977F/ AF supports an IBM XT/AT compatible parallel port (SPP), bi-directional parallel port (BPP), Enhanced Parallel Port (EPP), Extended Capabilities Parallel Port (ECP), Extension FDD mode (EXTFDD), Extension 2FDD mode (EXT2FDD) on the parallel port. Refer to the configuration registers for more information on disabling, power-down, and on selecting the mode of operation. Table 5-1 shows the pin definitions for different modes of the parallel port.
TABLE 5-1-1 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS HOST CONNECTOR 1 2-9 10 11 12 13 14 15 16 17 Notes: n : Active Low 1. Compatible Mode 2. High Speed Mode 3. For more information, refer to the IEEE 1284 standard. TABLE 5-1-2 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS HOST CONNECTOR 1 2 3 4 5 6 7 PIN NUMBER OF W83977F/ AF 36 31 30 29 28 27 26 PIN ATTRIBUTE O I/O I/O I/O I/O I/O I/O SPP nSTB PD0 PD1 PD2 PD3 PD4 PD5 PIN ATTRIBUTE --I I I I I --EXT2FDD --INDEX 2 TRAK02 WP2 RDATA2 DSKCHG2 --PIN ATTRIBUTE --I I I I I --EXTFDD --INDEX 2 TRAK02 WP2 RDATA2 DSKCHG2 --PIN NUMBER OF W83977F/ AF 36 31-26, 24-23 22 21 19 18 35 34 33 32 PIN ATTRIBUTE O I/O I I I I O I O O SPP nSTB PD<0:7> nACK BUSY PE SLCT nAFD nERR nINIT nSLIN EPP nWrite PD<0:7> Intr nWait PE Select nDStrb nError nInit nAStrb ECP nSTB, HostClk2 PD<0:7> nACK, PeriphClk2 BUSY, PeriphAck2 PEerror, nAckReverse2 SLCT, Xflag2 nAFD, HostAck2 nFault1, nPeriphRequest2 nINIT1, nReverseRqst2 nSLIN1 , ECPMode2
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PRELIMINARY
TABLE 5-1-2, continued HOST CONNECTOR 8 9 10 11 12 13 14 15 16 17 PIN NUMBER OF W83977F/ AF 24 23 22 21 19 18 35 34 33 32 PIN ATTRIBUTE I/O I/O I I I I O I O O SPP PD6 PD7 nACK BUSY PE SLCT nAFD nERR nINIT nSLIN PIN ATTRIBUTE OD OD OD OD OD OD OD OD OD OD EXT2FDD PIN ATTRIBUTE ----OD OD OD OD OD OD OD OD EXTFDD ----DSB2 MOB2 WD2 WE2 RWC2 HEAD2 DIR2 STEP2
MOA2 DSA2 DSB2 MOB2 WD2 WE2 RWC2 HEAD2 DIR2 STEP2
5.2
Enhanced Parallel Port (EPP)
A2 0 0 0 0 0 1 1 1 1 A1 0 0 1 1 1 0 0 1 1 A0 0 1 0 0 1 0 1 0 1 REGISTER Data port (R/W) Printer status buffer (Read) Printer control latch (Write) Printer control swapper (Read) EPP address port (R/W) EPP data port 0 (R/W) EPP data port 1 (R/W) EPP data port 2 (R/W) EPP data port 2 (R/W) NOTE 1 1 1 1 2 2 2 2 2
TABLE 5-2 PRINTER MODE AND EPP REGISTER ADDRESS
Notes: 1. These registers are available in all modes. 2. These registers are available only in EPP mode.
5.2.1 Data Swapper The system microprocessor can read the contents of the printer's data latch by reading the data swapper.
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PRELIMINARY
5.2.2 Printer Status Buffer The system microprocessor can read the printer status by reading the address of the printer status buffer. The bit definitions are as follows:
7 6 5 4 3 2 1 1 1 TMOUT ERROR SLCT PE ACK BUSY 0
Bit 7: This signal is active during data entry, when the printer is off-line during printing, when the print head is changing position, or during an error state. When this signal is active, the printer is busy and cannot accept data. Bit 6: This bit represents the current state of the printer's ACK signal. A 0 means the printer has received a character and is ready to accept another. Normally, this signal will be active for approximately 5 microseconds before BUSY stops. Bit 5: Logical 1 means the printer has detected the end of paper. Bit 4: Logical 1 means the printer is selected. Bit 3: Logical 0 means the printer has encountered an error condition. Bit 1, 2: These two bits are not implemented and are logic one during a read of the status register. Bit 0: This bit is valid in EPP mode only. It indicates that a 10 S time-out has occurred on the EPP bus. A logic 0 means that no time-out error has occurred; a logic 1 means that a time-out error has been detected. Writing a logic 1 to this bit will clear the time-out status bit; writing a logic 0 has no effect.
5.2.3 Printer Control Latch and Printer Control Swapper The system microprocessor can read the contents of the printer control latch by reading the printer control swapper. Bit definitions are as follows:
7 1 6 1 STROBE AUTO FD INIT SLCT IN IRQ ENABLE DIR 5 4 3 2 1 0
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Bit 7, 6: These two bits are a logic one during a read. They can be written. Bit 5: Direction control bit When this bit is a logic 1, the parallel port is in input mode (read); when it is a logic 0, the parallel port is in output mode (write). This bit can be read and written. In SPP mode, this bit is invalid and fixed at zero. Bit 4: A 1 in this position allows an interrupt to occur when ACK changes from low to high. Bit 3: A 1 in this bit position selects the printer. Bit 2: A 0 starts the printer (50 microsecond pulse, minimum). Bit 1: A 1 causes the printer to line-feed after a line is printed. Bit 0: A 0.5 microsecond minimum high active pulse clocks data into the printer. Valid data must be present for a minimum of 0.5 microseconds before and after the strobe pulse.
5.2.4 EPP Address Port The address port is available only in EPP mode. Bit definitions are as follows:
7 6 5 4 3 2 1 0
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write operation. The leading edge of IOW causes an EPP address write cycle to be performed, and the trailing edge of IOW latches the data for the duration of the EPP write cycle. PD0-PD7 ports are read during a read operation. The leading edge of IOR causes an EPP address read cycle to be performed and the data to be output to the host CPU.
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PRELIMINARY
5.2.5 EPP Data Port 0-3 These four registers are available only in EPP mode. Bit definitions of each data port are as follows:
7 6 5 4 3 2 1 0
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (noninverting) and output to the ports PD0-PD7 during a write operation. The leading edge of IOW causes an EPP data write cycle to be performed, and the trailing edge of IOW latches the data for the duration of the EPP write cycle. During a read operation, ports PD0-PD7 are read, and the leading edge of IOR causes an EPP read cycle to be performed and the data to be output to the host CPU. 5.2.6 Bit Map of Parallel Port and EPP Registers
REGISTER Data Port (R/W) Status Buffer (Read) Control Swapper (Read) Control Latch (Write) EPP Address Port R/W) EPP Data Port 0 (R/W) EPP Data Port 1 (R/W) EPP Data Port 2 (R/W) EPP Data Port 3 (R/W)
7 PD7
6 PD6
5 PD5 PE 1 DIR PD5 PD5 PD5 PD5 PD5
4 PD4 SLCT IRQEN IRQ PD4 PD4 PD4 PD4 PD4
3 PD3
2 PD2 1
1 PD1 1
0 PD0 TMOUT
BUSY
1 1 PD7 PD7 PD7 PD7 PD7
ACK
1 1 PD6 PD6 PD6 PD6 PD6
ERROR
SLIN SLIN PD3 PD3 PD3 PD3 PD3
INIT INIT
PD2 PD2 PD2 PD2 PD2
AUTOFD AUTOFD
PD1 PD1 PD1 PD1 PD1
STROBE STROBE
PD0 PD0 PD0 PD0 PD0
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5.2.7 EPP Pin Descriptions EPP NAME nWrite PD<0:7> Intr nWait PE Select nDStrb nError nInits nAStrb TYPE O I/O I I I I O I O O EPP DESCRIPTION Denotes an address or data read or write operation. Bi-directional EPP address and data bus. Used by peripheral device to interrupt the host. Inactive to acknowledge that data transfer is completed. Active to indicate that the device is ready for the next transfer. Paper end; same as SPP mode. Printer selected status; same as SPP mode. This signal is active low. It denotes a data read or write operation. Error; same as SPP mode. This signal is active low. When it is active, the EPP device is reset to its initial operating mode. This signal is active low. It denotes an address read or write operation.
5.2.8 EPP Operation When the EPP mode is selected in the configuration register, the standard and bi-directional modes are also available. The PDx bus is in the standard or bi-directional mode when no EPP read, write, or address cycle is currently being executed. In this condition all output signals are set by the SPP Control Port and the direction is controlled by DIR of the Control Port. A watchdog timer is required to prevent system lockup. The timer indicates that more than 10 S have elapsed from the start of the EPP cycle to the time WAIT is deasserted. The current EPP cycle is aborted when a time-out occurs. The time-out condition is indicated in Status bit 0. 5.2.8.1 EPP Operation The EPP operates on a two-phase cycle. First, the host selects the register within the device for subsequent operations. Second, the host performs a series of read and/or write byte operations to the selected register. Four operations are supported on the EPP: Address Write, Data Write, Address Read, and Data Read. All operations on the EPP device are performed asynchronously. 5.2.8.2 EPP Version 1.9 Operation The EPP read/write operation can be completed under the following conditions: a. If the nWait is active low, when the read cycle (nWrite inactive high, nDStrb/nAStrb active low) or write cycle (nWrite active low, nDStrb/nAStrb active low) starts, the read/write cycle proceeds normally and will be completed when nWait goes inactive high. b. If nWait is inactive high, the read/write cycle will not start. It must wait until nWait changes to active low, at which time it will start as described above. 5.2.8.3 EPP Version 1.7 Operation The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the read/write cycle starts, however, it will not terminate until nWait changes from active low to inactive high.
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PRELIMINARY
5.3
Extended Capabilities Parallel (ECP) Port
This port is software and hardware compatible with existing parallel ports, so it may be used as a
standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward (host to peripheral) and reverse (peripheral to host) directions. Small FIFOs are used in both forward and reverse directions to improve the maximum bandwidth requirement. The size of the FIFO is 16 bytes. The ECP port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed. The ECP port supports run-length-encoded (RLE) decompression (required) in hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Hardware support for compression is optional. For more information about the ECP Protocol, refer to the Extended Capabilities Port Protocol and ISA Interface Standard. 5.3.1 ECP Register and Mode Definitions NAME data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr ADDRESS Base+000h Base+000h Base+001h Base+002h Base+400h Base+400h Base+400h Base+400h Base+401h Base+402h I/O R/W R/W R R/W R/W R/W R/W R R/W R/W ECP MODES 000-001 011 All All 010 011 110 111 111 All FUNCTION Data Register ECP FIFO (Address) Status Register Control Register Parallel Port Data FIFO ECP FIFO (DATA) Test FIFO Configuration Register A Configuration Register B Extended Control Register
Note: The base addresses are specified by CR23, which are determined by configuration register or hardware setting.
MODE 000 001 010 011 100 101 110 111 SPP mode PS/2 Parallel Port mode Parallel Port Data FIFO mode ECP Parallel Port mode
DESCRIPTION
EPP mode (If this option is enabled in the CR9 and CR0 to select ECP/EPP mode) Reserved Test mode Configuration mode
Note: The mode selection bits are bit 7-5 of the Extended Control Register.
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5.3.2 Data and ecpAFifo Port Modes 000 (SPP) and 001 (PS/2) (Data Port) During a write operation, the Data Register latches the contents of the data bus on the rising edge of the input. The contents of this register are output to the PD0-PD7 ports. During a read operation, ports PD0-PD7 are read and output to the host. The bit definitions are as follows:
7 6 5 4 3 2 1 0
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
Mode 011 (ECP FIFO-Address/RLE) A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this register is defined only for the forward direction. The bit definitions are as follows:
7 6 5 4 3 2 1 0
Address or RLE
Address/RLE
5.3.3 Device Status Register (DSR) These bits are at low level during a read of the Printer Status Register. The bits of this status register are defined as follows:
7 6 5 4 3 2 1 1 1 0 1
nFault Select PError nAck nBusy
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Bit 7: This bit reflects the complement of the Busy input. Bit 6: This bit reflects the nAck input. Bit 5: This bit reflects the PError input. Bit 4: This bit reflects the Select input. Bit 3: This bit reflects the nFault input. Bit 2-0: These three bits are not implemented and are always logic one during a read.
5.3.4 Device Control Register (DCR) The bit definitions are as follows:
7 1 6 1 strobe autofd nInit SelectIn ackIntEn Direction 5 4 3 2 1 0
Bit 6, 7: These two bits are logic one during a read and cannot be written. Bit 5: This bit has no effect and the direction is always out if mode = 000 or mode = 010. Direction is valid in all other modes. 0 the parallel port is in output mode. 1 the parallel port is in input mode. Bit 4: Interrupt request enable. When this bit is set to a high level, it may be used to enable interrupt requests from the parallel port to the CPU due to a low to high transition on the ACK input. Bit 3: This bit is inverted and output to the SLIN output. 0 The printer is not selected. 1 The printer is selected. Bit 2: This bit is output to the INIT output. Bit 1: This bit is inverted and output to the AFD output. Bit 0: This bit is inverted and output to the STB output.
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PRELIMINARY
5.3.5 cFifo (Parallel Port Data FIFO) Mode = 010 This mode is defined only for the forward direction. The standard parallel port protocol is used by a hardware handshake to the peripheral to transmit bytes written or DMAed from the system to this FIFO. Transfers to the FIFO are byte aligned. 5.3.6 ecpDFifo (ECP Data FIFO) Mode = 011 When the direction bit is 0, bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned. When the direction bit is 1, data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO. Reads or DMAs from the FIFO will return bytes of ECP data to the system. 5.3.7 tFifo (Test FIFO Mode) Mode = 110 Data bytes may be read, written, or DMAed to or from the system to this FIFO in any direction. Data in the tFIFO will not be transmitted to the parallel port lines. However, data in the tFIFO may be displayed on the parallel port data lines. 5.3.8 cnfgA (Configuration Register A) Mode = 111 This register is a read-only register. When it is read, 10H is returned. This indicates to the system that this is an 8-bit implementation. 5.3.9 cnfgB (Configuration Register B) Mode = 111
The bit definitions are as follows: 7 6 5 4 3 2 1 1 1 0 1
IRQx 0 IRQx 1 IRQx 2 intrValue compress Bit 7: This bit is read-only. It is at low level during a read. This means that this chip does not support hardware RLE compression. Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts.
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PRELIMINARY
Bit 5-3: Reflect the IRQ resource assigned for ECP port. cnfgB[5:3] 000 001 010 011 100 101 110 111 IRQ resource reflect other IRQ resources selected by PnP register (default) IRQ7 IRQ9 IRQ10 IRQ11 IRQ14 IRQ15 IRQ5
Bit 2-0: These five bits are at high level during a read and can be written. 5.3.10 ecr (Extended Control Register) Mode = all This register controls the extended ECP parallel port functions. The bit definitions are follows:
7 6 5 4 3 2 1 0
empty full service Intr dmaEn nErrIntrEn MODE MODE MODE
Bit 7-5: These bits are read/write and select the mode. 000 001 Standard Parallel Port mode. The FIFO is reset in this mode. PS/2 Parallel Port mode. This is the same as 000 except that direction may be used to tri-state the data lines and reading the data register returns the value on the data lines and not the value in the data register. Parallel Port FIFO mode. This is the same as 000 except that bytes are written or DMAed to the FIFO. FIFO data are automatically transmitted using the standard parallel port protocol. This mode is useful only when direction is 0. ECP Parallel Port Mode. When the direction is 0 (forward direction), bytes placed into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and auto transmitted to the peripheral using ECP Protocol. When the direction is 1 (reverse direction), bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo. Selects EPP Mode. In this mode, EPP is activated if the EPP mode is selected. Reserved. Test Mode. The FIFO may be written and read in this mode, but the data will not be transmitted on the parallel port. Configuration Mode. The confgA and confgB registers are accessible at 0x400 and 0x401 in this mode.
010
011
100 101 110 111
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PRELIMINARY
Bit 4: Read/Write (Valid only in ECP Mode) 1 Disables the interrupt generated on the asserting edge of nFault. 0 Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted (interrupt) an interrupt will be generated and this bit is written from a 1 to 0. Bit 3: Read/Write 1 Enables DMA. 0 Disables DMA unconditionally. Bit 2: Read/Write 1 Disables DMA and all of the service interrupts. 0 Enables one of the following cases of interrupts. When one of the service interrupts has occurred, the serviceIntr bit is set to a 1 by hardware. This bit must be reset to 0 to re-enable the interrupts. Writing a 1 to this bit will not cause an interrupt. (a) dmaEn = 1: During DMA this bit is set to a 1 when terminal count is reached. (b) dmaEn = 0 direction = 0: This bit is set to 1 whenever there are writeIntr Threshold or more bytes free in the FIFO. (c) dmaEn = 0 direction = 1: This bit is set to 1 whenever there are readIntr Threshold or more valid bytes to be read from the FIFO. Bit 1: Read only 0 The FIFO has at least 1 free byte. 1 The FIFO cannot accept another byte or the FIFO is completely full. Bit 0: Read only 0 The FIFO contains at least 1 byte of data. 1 The FIFO is completely empty. 5.3.11Bit Map of ECP Port Registers D7 data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr
PD7 Addr/RLE nBusy 1
D6
PD6
D5
PD5
D4
PD4
D3
PD3
D2
PD2
D1
PD1
D0
PD0
NOTE
2
Address or RLE field nAck 1 PError Directio Select ackIntEn nFault SelectIn 1 nInit 1 autofd 1 strobe
1 1 2 2 2
Parallel Port Data FIFO ECP Data FIFO Test FIFO 0 compress 0 intrValue MODE 0 1 1 1 nErrIntrEn 0 1 dmaEn 0 1 serviceIntr 0 1 full 0 1 empty
Notes: 1. These registers are available in all modes. 2. All FIFOs use one common 16-byte FIFO.
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PRELIMINARY
5.3.12 ECP Pin Descriptions NAME nStrobe (HostClk) TYPE O DESCRIPTION The nStrobe registers data or address into the slave on the asserting edge during write operations. This signal handshakes with Busy. These signals contains address or data or RLE data. This signal indicates valid data driven by the peripheral when asserted. This signal handshakes with nAutoFd in reverse. This signal deasserts to indicate that the peripheral can accept data. It indicates whether the data lines contain ECP command information or data in the reverse direction. When in reverse direction, normal data are transferred when Busy (PeriphAck) is high and an 8-bit command is transferred when it is low. This signal is used to acknowledge a change in the direction of the transfer (asserted = forward). The peripheral drives this signal low to acknowledge nReverseRequest. The host relies upon nAckReverse to determine when it is permitted to drive the data bus. Indicates printer on line. Requests a byte of data from the peripheral when it is asserted. This signal indicates whether the data lines contain ECP address or data in the forward direction. When in forward direction, normal data are transferred when nAutoFd (HostAck) is high and an 8-bit command is transferred when it is low. Generates an error interrupt when it is asserted. This signal is valid only in the forward direction. The peripheral is permitted (but not required) to drive this pin low to request a reverse transfer during ECP Mode. This signal sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. This signal is always deasserted in ECP mode.
PD<7:0> nAck (PeriphClk) Busy (PeriphAck)
I/O I I
PError (nAckReverse)
I
Select (Xflag) nAutoFd (HostAck)
I O
nFault (nPeriphRequest)
I
nInit (nReverseRequest)
O
nSelectIn (ECPMode)
O
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PRELIMINARY
5.3.13 ECP Operation The host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol before ECP operation. After negotiation, it is necessary to initialize some of the port bits. The following are required: (a) Set direction = 0, enabling the drivers. (b) Set strobe = 0, causing the nStrobe signal to default to the deasserted state. (c) Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state. (d) Set mode = 011 (ECP Mode) ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo, respectively. 5.3.13.1 Mode Switching Software will execute P1284 negotiation and all operations prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ECP port only in the data transfer phase (mode 011 or 010). If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001 it can only be switched into mode 000 or 001. The direction can be changed only in mode 001. When in extended forward mode, the software should wait for the FIFO to be empty before switching back to mode 000 or 001. In ECP reverse mode the software waits for all the data to be read from the FIFO before changing back to mode 000 or 001. 5.3.13.2 Command/Data ECP mode allows the transfer of normal 8-bit data or 8-bit commands. In the forward direction, normal data are transferred when HostAck is high and an 8-bit command is transferred when HostAck is low. The most significant bits of the command indicate whether it is a run-length count (for compression) or a channel address. In the reverse direction, normal data are transferred when PeriphAck is high and an 8-bit command is transferred when PeriphAck is low. The most significant bit of the command is always zero. 5.3.13.3 Data Compression The W83977F/ AF supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Note that the odd (RLE) compression in hardware is not supported. In order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo. 5.3.14 FIFO Operation The FIFO threshold is set in configuration register 5. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. After a reset, the FIFO is disabled.
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PRELIMINARY
5.3.15 DMA Transfers DMA transfers are always to or from the ecpDFifo, tFifo, or CFifo. The DMA uses the standard PC DMA services. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA will empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the DMA controller is reached, an interrupt is generated and serviceIntr is asserted, which will disable the DMA.
5.3.16 Programmed I/O (NON-DMA) Mode The ECP or parallel port FIFOs can also be operated using interrupt driven programmed I/O. Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located at 400H, or to/from the tFifo at 400H. The host must set the direction, state, dmaEn = 0 and serviceIntr = 0 in the programmed I/O transfers. The ECP requests programmed I/O transfers from the host by activating the IRQ pin. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode.
5.4
Extension FDD Mode (EXTFDD)
In this mode, the W83977F/ AF changes the printer interface pins to FDC input/output pins, allowing the user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. The pin assignments for the FDC input/output pins are shown in Table 5-1. After the printer interface is set to EXTFDD mode, the following occur: (1) Pins MOB and DSB will be forced to inactive state. (2) Pins DSKCHG, RDATA , WP, TRAK0, INDEX will be logically ORed with pins PD4-PD0 to serve as input signals to the FDC. (3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for FDD open drain/collector output. (4) If the parallel port is set to EXTFDD mode after the system has booted DOS or another operating system, a warm reset is needed to enable the system to recognize the extension floppy drive.
5.5 Extension 2FDD Mode (EXT2FDD)
In this mode, the W83977F/ AF changes the printer interface pins to FDC input/output pins, allowing the user to install two external floppy disk drives through the DB-25 printer connector to replace internal floppy disk drives A and B. The pin assignments for the FDC input/output pins are shown in Table5-1. After the printer interface is set to EXTFDD mode, the following occur: (1) Pins MOA , DSA , MOB, and DSB will be forced to inactive state. (2) Pins DSKCHG, RDATA , WP, TRAK0, and INDEX will be logically ORed with pins PD4-PD0 to serve as input signals to the FDC. (3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for FDD open drain/collector output. (4) If the parallel port is set to EXT2FDD mode after the system has booted DOS or another operating system, a warm reset is needed to enable the system to recognize the extension floppy drive.
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PRELIMINARY
6. REAL-TIME CLOCK (RTC) AND "ON-NOW" CONTROL
The RTC with 242 bytes of RAM is a low-power device that provides a time-of-day clock in various formats, and a calendar with century register. It has two alarms and three programmable interrupts. It is also equipped with external battery backup capability for keeping time and saving RAM data under power-failure situation. The RTC software is compatible with the MC146818 Clock chip. The "On-Now" Control enables PC to be powered on by several trigger events, a telephone ring for example. Also, it allows a safely controlled power-off procedure executed in an orderly fashion.
6.1 REGISTER ADDRESS MAP
Table 6.1.1, table 6.1.2, and table 6.1.3 show the register map of RTC and "On-Now". These registers are separated into three banks: Bank 0, Bank 1, and Bank 2. Bank 0 contains 10 bytes of time, calendar, and alarm A data, four bytes of control/status registers, and 114 bytes of general purpose user RAM. TABLE 6.1.1 - REAL TIME CLOCK ADDRESS MAP BANK 0 ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh-7Fh REGISTER TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W REGISTER FUNCTION Register 00h : Seconds Register 01h : Seconds Alarm A Register 02h : Minutes Register 03h : Minutes Alarm A Register 04h : Hours Register 05h : Hours Alarm A Register 06h : Day of Week Register 07h : Date of Month Register 08h: Month Register 09h : Year Register 0Ah : Control Register Register 0Bh : Control Register (Bit 0 is Read only) Register 0Ch : Status Register Register 0Dh : Status Register Register 0Eh-7Fh : User RAM
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PRELIMINARY
In Bank 1, there are 128 bytes of general purpose user RAM, as shown in table 6.1.2. TABLE 6.1.2 - REAL TIME CLOCK ADDRESS MAP BANK 1 ADDRESS 00h-7Fh REGISTER TYPE R/W REGISTER FUNCTION Register 0h-7Fh : user RAM
Bank 2 has 13 registers, 1 Century register, 8 Alarm B registers and 4 control/status registers for "OnNow" function. TABLE 6.1.3 - REAL TIME CLOCK "ON-NOW" ADDRESS MAP BANK 2 ADDRESS 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch REGISTER TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W REGISTER FUNCTION Register 40h : Centuries Register 41h : Seconds Alarm B Register 42h : Minutes Alarm B Register 43h : Hours Alarm B Register 44h : Day of Week Alarm B Register 45h : Date of Month Alarm B Register 46h : Month Alarm B Register 47h : Year Alarm B Register 48h : Century Alarm B Register 49h : "On-Now" Control Register 1 Register 4Ah : "On-Now" Control Register 2 Register 4Bh : "On-Now" Status Register 3 Register 4Ch : "On-Now" Control/Status Register 4
Time, Calendar, Alarm A, and Alarm B data Modes REGISTER LOCATION Register 00h Register 01h Register 02h Register 03h Register 04h Seconds Sec. Alarm A Minutes Min. Alarm A Hours FUNCTION RANGE(DATA MODE) BINARY 00h-3Bh 00h-3Bh 00h-3Bh 00h-3Bh 01h-0Ch(AM) BCD 00h-59h 00h-59h 00h-59h 00h-59h 01h-12h(AM) 81h-92h(PM) 00h-23h 08h 08h EXAMPLE BINARY 1Eh 1Eh 1Eh 1Eh 08h BCD 30h 30h 30h 30h 08h
(12-Hour Mode) 81h-8Ch(PM) (24-Hour Mode) 00h-17h
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PRELIMINARY
Time, Calendar, Alarm A, and Alarm B data Modes continued REGISTER LOCATION Register 05h Hours Alarm A FUNCTION RANGE(DATA MODE) BINARY 01h-0Ch(AM) (12-Hour Mode) 81h-8Ch(PM) (24-Hour Mode) 00h-17h Register 06h Register 07h Register 08h Register 09h Register 40h Register 41h Register 42h Register 43h Day of Week Date of Month Month Year Century Sec. Alarm B Min. Alarm B Hours Alarm B 01h-07h 01h-1Fh 01h-0Ch 00h-63h 00h-63h 00h-3Bh 00h-3Bh 01h-0Ch(AM) BCD 01h-12h(AM) 81h-92h(PM) 00h-23h 01h-07h 01h-31h 01h-12h 00h-99h 00h-99h 00h-59h 00h-59h 01h-12h(AM) 81h-92h(PM) 00h-23h 01h-07h 01h-31h 01h-12h 00h-99h 00h-99h 08h 02h 04h 07h 61h 13h 08h 02h 04h 07h 97h 19h 08h 02h 04h 07h 61h 13h 1Eh 1Eh 08h 08h 02h 04h 07h 97h 19h 30h 30h 08h EXAMPLE BINARY 08h BCD 08h
(12-Hour Mode) 81h-8Ch(PM) (24-Hour Mode) 00h-17h Register 44h Register 45h Register 46h Register 47h Register 48h Day of Week Alarm B Date of Month Alarm B Month Alarm B 01h-0Ch Year Alarm B Century Alarm B 00h-63h 00h-63h 01h-1Fh 01h-07h
6.2 Update Cycle
The RTC executes an update cycle once per second. It is in an update cycle when RTC updates the contents of the clock and calendar registers. In the meantime, RTC also compares each alarm byte with corresponding timer byte and generates an alarm flag if a match or a don't care condition (0C0h) is present in the alarm register. The update-in-progress bit (UIP) in register A pulses high once per second. The update cycle occurs 244S after the UIP bit goes high. This bit is cleared and the update-ended flag (UF) is set in the end of an update cycle.
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PRELIMINARY
UPDATE CYCLE TIME TABLE UIP BIT 1 0 UPDATE CYCLE TIME (TUC) 1984S BEFORE UPDATE CYCLE TIME (TBUC MIN) 244S
Update Period and UIP Timing
Update Period(1 Second)
t BUC
t UC
6.3 REGISTERS
The RTC has four control/status registers. They are accessible at all times. 6.3.1 Register 0Ah * All bits are unaffected by RESET. * Register A is a read/write register except bit 7 (UIP is read only). BIT NAME 7 UIP 6 DV2 5 DV1 4 DV0 3 RS3 2 RS2 1 RS1 0 RS0
UIP : (read only) When UIP is 1, an update cycle is in progress. The UIP is cleared in the end of an update cycle and when the SET bit in register B is 1.
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PRELIMINARY
DV[2:0] : Divider Control These three bits are used to control divider and 32KHz oscillator. TIME-BASE FREQUENCY 32.768KHZ 32.768KHZ 32.768KHZ 32.768KHZ 32.768KHZ DV2 0 0 0 1 1 DV1 0 1 1 0 1 DV0 X 0 1 X X OPERATION MODE NO YES NO NO NO DIVIDER RESET YES
RS[3:0] : Periodic Interrupt Rate PERIODIC INTERRUPT RATE TABLE RS[3:0] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 TIME BASE None 3.90625mS / 256Hz 7.8125mS / 128Hz 122.070S / 8.192KHz 244.141S / 4.096KHz 488.281S / 2.048KHz 976.562S / 1.024KHz 1.953125mS / 512Hz 3.90625mS / 256Hz 7.8125mS / 128Hz 15.625ms / 64Hz 31.25ms / 32Hz 62.5ms / 16Hz 125ms / 8Hz 250ms / 4Hz 500ms / 2Hz
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PRELIMINARY
6.3.2 Register 0Bh (Read/Write) BIT NAME SET When the SET bit is set, any occurring update cycle is aborted and registers (Register 00h~09h, Register (40h~48h) may be modified without entering an update cycle. When this bit is cleared, the update cycle function occurs once per second. This bit is not affected by any other internal functions or by a RESET. PE A "1" on the periodic interrupt enable bit enables the periodic interrupt flag (PF) bit in Register 0Ch to assert an interrupt. A "0" on this bit blocks the IRQ output from being driven by a periodic interrupt. This bit can not be modified by any internal function, but it may be cleared by a RESET. AE A "1" on the enable bit of alarm A enables the alarm A flag (AF) bit in Register 0Ch to assert an interrupt. A "0" on this bit prohibits alarm A interrupt. The RESET signal clears AE to "0". This bit can not be modified by any internal function. UE A "1" on this bit enables the update-ended flag (UF) bit in register C to assert an interrupt. A "0" on this bit prohibits update-ended interrupt. The UE bit is cleared by setting the SET bit or by a RESET. DM The data mode bit determines whether time and calendar updates are in binary format or in binarycoded-decimal (BCD) format. A "1" on this bit means binary format. A "0" on this bit means BCD format. This bit can not be modified by a RESET or any internal function. 24/12 A "1" on this bit selects 24-hour mode for the time-of-day function. A "0" on this bit selects 12-hour mode. This bit can not be modified by a RESET or any internal function. DSE A "1" on this bit allows two special updates: * On the last Sunday of April, the time increments from 1:59:59 AM to 3:00:00 AM. * On the last Sunday of October, the time decrements from 1:59:59 AM to 1:00:00 AM. A "0" on this bit disables these special updates. DSE can not be changed by any internal operation or a RESET.
(Note: RTC IRQ is ultimately controlled by Logical Device 4-CR70 and Logical Device 4-CR71. These two registers must be set properly if RTC IRQ is needed)
7 SET
6 PE
5 AE
4 UE
3 Reserved
2 DM
1 12/24
0 DSE
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W83977F/ W83977AF
PRELIMINARY
6.3.3 Register 0Ch (Read only) BIT NAME IRQF The interrupt request flag is set to a "1" if one or more of following cases are true: PF*PE = "1" AF*AE = "1" UF*UE = "1" (i.e., IRQF = PF*PE + AF*AE + UF*UE) Any time the IRQF bit is a "1", the IRQ is asserted (provided LD4-CR70 and LD4-CR71 are set properly). All flags are cleared by reading the register or by a RESET. PF The periodic interrupt flag is set to "1" when a rising edge is detected on the selected tap of the divider chain(RS[3:0] of register A). PF is set to a "1" regardless of the state of PE bit. This bit is cleared by a RESET or when this register is read. AF A "1" on this bit indicates that the current time has reached the alarm time setting (alarm A). A RESET or a read of this register clears this bit. UF The update-ended interrupt flag bit is set after the end of each update cycle. This bit is cleared by a RESET or when this bit is read. Bit 3 - Bit 0 These bits are reserved and all read "0". 7 IRQF 6 PF 5 AF 4 UF 3 0 2 0 1 0 0 0
6.3.4 Register D (Read only) BIT NAME VRT The valid RAM and time bit. A "0" appears on this bit when the external battery is removed or at lowvoltage during power-failure situation, indicating the data integrity of the real time clock, "On-Now" logic, and storage registers is not guaranteed. This bit can only be set by reading this register, and is not affected by a RESET. 7 VRT 6 0 5 0 4 0 3 0 2 0 1 0 0 0
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PRELIMINARY
6.4 "On-Now" Control
The "On-Now" Control function is built in RTC. It enables the PC to be powered on automatically from triggers of various events, and to be powered off in an orderly controlled fashion. The "On-Now" works at all times even when the system power is switch-off or disconnected. It detects several external events to control system power supply On/Off properly (e.g. telephone ring, panel switch-off). It also controls the signal (PSCTRL ) to turn the power supply on or off.
6.5 Power-On Events
The "On-Now" Control turns on power supply when one of the following events occurs: * Panel Switch "turned on" * Telephone is ringing * Ring-In detection signal comes from a modem * Keyboard/Mouse is stroked/moved * Power-wake-up input goes from high to low. * PSCTRL active when power returns after a power-failure occurs.
(Note: Panel-Switch has a debounce circuit which is clocked by RTC 32.768KHz oscillator. The "On-Now" control will not function properly if this oscillator fails to work and PC can not be powered-on consequently)
6.6 Power-Off Events
* Panel Switch "turned off" * Power-off under software control * Power-failure event * Override Power off: Panel switch is pushed for at least 4 seconds, then the system will be forced to turn off immediately
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PRELIMINARY
6.7 Registers
6.7.1 BIT NAME On-Now 7 PF Register 1 (Bank2 Register 49h) 6 CLPOST 5 SPOFC 4 DPSCA 3 CLRSMI 2 SMIMD 1 0
PHRIDM DPODTM
PF (Power Failure) The PF is set when a power-failure occurs. This bit is cleared by writing a "1" to it. CLPOST (Clear Panel-switch-off-Save Timer) This bit is self-cleared after writing an "1" to it. If it is set, Panel-switch-off-Save timer is stopped and cleared. SPOFC (Software Power-Off Command) This bit is self-cleared after writing an "1" to it. If it is set, the PSCTRL goes inactive immediately. DPSCA (Disable Power Supply Control Activation) This bit is set as long as PF is set. When set, it disables all PSCTRL activation events except PanelSwitch- On event. CLSMI (Clear SMI ) This bit is self-cleared after writing an "1" to it. If it is set, SMI is cleared to its inactive state. This bit is used to clear SMI when SMIMD is set. SMIMD ( SMI Mode) If it is set, SMI is level-sensitive. Once SMI goes active, it keeps active until CLSMI is set. Writing a "0" to this bit sets SMI to be edge-triggered. PHRIDM (PHRI Detection Mode) A "1" on this bit sets PHRI detection mode to be on falling edge. A "0" on this bit sets PHRI detection mode to be on a pulse train of frequency greater than 11Hz and lasts for 0.2 second. DPODTM (Disable Power Off Delay Timer ) If set, Panel Switch Power-Off Delay Timer is stopped. If reset, Panel Switch Power-Off Delay Timer counts down continuously.
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PRELIMINARY
6.7.2 On-Now Register 2 (Bank2 Register 4Ah) BIT NAME 7 MCLKE 6 KCLKE 5 RIBE 4 RIAE 3 PHRIE 2 1 0 ALARMBE
PWAKI2E PWAKI1E
MCLKE (Mouse Clock Enable) Logical 1 on this bit, a falling edge transition on MCLK asserts PSCTRL . KCLKE (Keyboard Clock Enable) Logical 1 on this bit, a falling edge transition on KCLK asserts PSCTRL . RIBE (RI B Enable) Logical 1 on this bit, a falling edge transition on RIB asserts PSCTRL . RIAE (RI A Enable) Logical 1 on this bit, a falling edge transition on RIA asserts PSCTRL . PHRIE (PHRI Enable) Logical 1 on this bit, a falling edge transition on PHRI asserts PSCTRL . PWAKI2E (Power Wake-up Input 2 Enable) Logical 1 on this bit, a falling edge transition on PWAKIN2 asserts PSCTRL . PWAKI1E (Power Wake-up Input 1 Enable) Logical 1 on this bit, a falling edge transition on PWAKIN1 asserts PSCTRL . ALARMBE (Alarm B Enable) Logical 1 on this bit, the alarm B reaches its predetermined time asserts PSCTRL .
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PRELIMINARY
6.7.3 "On-Now" Register 3 (Bank2 Register 4Bh) BIT NAME 7 PHRIST 6 5 4 3 RIBD 2 RIAD 1 PHRID 0 ALMBD
Reserved PSPOFD PSPOFTD
This register is read only except bit 5. PHRIST (PHRI Status) This bit holds the current value of PHRI . PSPOFD (Panel Switch Power-Off Detect) Logical 1 on this bit, a Panel-Switch-Off event is detected. Logical 0 on this bit, there is no Panel-Switch-Off event. PSOFTD (Panel Switch Power-Off Delay Timer Detect) This bit is set when Panel Switch Power-Off Delay Timer reaches its terminal count. This bit is cleared by reading this register. RIBD (RI B Detect) A falling edge transition on RIB asserts this bit. This bit is cleared by reading this register. RIAD (RI A Detect) A falling edge transition on RIA asserts this bit. This bit is cleared by reading this register. PHRID (PHRI Detect) A falling edge transition on PHRI asserts this bit. This bit is cleared by reading this register. ALMBD (Alarm B Detect) Logical 1 on this bit, the alarm B when reaching its preset time asserts this bit. This bit is cleared by reading this register.
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PRELIMINARY
6.7.4 "On-Now" Register 4 (Bank2 Register 4Ch) BIT NAME 7 6 5 4 Reserved 3 MCLKD 2 KCLKD 1 0
PSOFDS1 PSOFDS0 INVSMI
PWAKI2D PWAKI1D
This register is read only except bits 5, 6 and 7. PSOFDS1, PSOFDS0 These two bits decide the delay time between panel switch power off event and power supply off. 00 : 0 second. 01 : 5 seconds. 10 : 13 seconds. 11 : 21 seconds. INVSMI Logical 1 on this bit, nSMI is active low and goes high-Z when dis-asserted. Logical 0 on this bit, nSMI is active high and goes high-Z when dis-asserted. MCLKD (MCLK Detect) A falling edge transition on MCLK asserts this bit. This bit is cleared by reading this register. KCLKD (KCLK Detect) A falling edge transition on KCLK asserts this bit. This bit is cleared by reading this register. PWAKI2D (PWAKIN2 Detect) A falling edge transition on PWAKIN2 asserts this bit. This bit is cleared by reading this register. PWAKI1D (PWAKIN1 Detect) A falling edge transition on PWAKIN1 asserts this bit. This bit is cleared by reading this register.
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PRELIMINARY
7. KEYBOARD CONTROLLER
The KBC (8042 with licensed KB BIOS) circuit of W83977F/ AF is designed to provide the functions needed to interface a CPU with a keyboard and/or a PS/2 mouse, and can be used with IBM(R)compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. Then, the controller will assert an interrupt to the system when data are placed in its output buffer. The keyboard and PS/2 mouse are required to acknowledge all data transmissions. No transmission should be sent to the keyboard or PS/2 mouse until an acknowledge is received for the previous data byte.
P24 P25 P21 KINH P17 P20 P27
KIRQ MIRQ GATEA20 KBRST KDAT KCLK
8042
GP I/O PINS Multiplex I/O PINS
P10 P26 T0
P12~P16
P23 T1 P22 P11
MCLK
MDAT
Keyboard and Mouse Interface
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PRELIMINARY
7.1 Output Buffer
The output buffer is an 8-bit read-only register at I/O address 60H (Default, PnP programmable I/O address LD5-CR60 and LD5-CR61). The keyboard controller uses the output buffer to send the scan code received from the keyboard and data bytes required by commands to the system. The output buffer can only be read when the output buffer full bit in the register is "1".
7.2
Input Buffer
The input buffer is an 8-bit write-only register at I/O address 60H or 64H (Default, PnP programmable I/O address LD5-CR60, LD5-CR61, LD5-CR62, and LD5-CR63). Writing to address 60H sets a flag to indicate a data write; writing to address 64H sets a flag to indicate a command write. Data written to I/O address 60H is sent to keyboard (unless the keyboard controller is expecting a data byte) through the controller's input buffer only if the input buffer full bit in the status register is 0 .
7.3
Status Register
The status register is an 8-bit read-only register at I/O address 64H (Default, PnP programmable I/O address LD5-CR62 and LD5-CR63), that holds information about the status of the keyboard controller and interface. It may be read at any time. BIT 0 1 2 BIT FUNCTION Output Buffer Full Input Buffer Full System Flag DESCRIPTION 0: Output buffer empty 1: Output buffer full 0: Input buffer empty 1: Input buffer full This bit may be set to 0 or 1 by writing to the system flag bit in the command byte of the keyboard controller. It defaults to 0 after a power-on reset. 0: Data byte 1: Command byte 0: Keyboard is inhibited 1: Keyboard is not inhibited 0: Auxiliary device output buffer empty 1: Auxiliary device output buffer full 0: No time-out error 1: Time-out error 0: Odd parity 1: Even parity (error)
3 4 5 6 7
Command/Data Inhibit Switch Auxiliary Device Output Buffer General Purpose Timeout Parity Error
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7.4
Commands
COMMAND 20h 60h FUNCTION Read Command Byte of Keyboard Controller Write Command Byte of Keyboard Controller
BIT 7 6 5 4 3 2 1 0 Reserved IBM Keyboard Translate Mode Disable Auxiliary Device Disable Keyboard Reserve System Flag Enable Auxiliary Interrupt Enable Keyboard Interrupt BIT DEFINITION
A4h
Test Password Returns 0Fah if Password is loaded Returns 0F1h if Password is not loaded
A5h A6h A7h A8h A9h
Load Password Load Password until a "0" is received from the system Enable Password Enable the checking of keystrokes for a match with the password Disable Auxiliary Device Interface Enable Auxiliary Device Interface Interface Test
BIT 00 01 02 03 04 BIT DEFINITION No Error Detected Auxiliary Device "Clock" line is stuck low Auxiliary Device "Clock" line is stuck high Auxiliary Device "Data" line is stuck low Auxiliary Device "Data" line is stuck low
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7.4 Commands, continued COMMAND AAh ABh Self-test Returns 055h if self test succeeds Interface Test
BIT 00 01 02 03 04 BIT DEFINITION No Error Detected Keyboard "Clock" line is stuck low Keyboard "Clock" line is stuck high Keyboard "Data" line is stuck low Keyboard "Data" line is stuck high
FUNCTION
ADh AEh C0h C1h C2h D0h D1h D2h D3h D4h E0h FXh
Disable Keyboard Interface Enable Keyboard Interface Read Input Port(P1) and send data to the system Continuously puts the lower four bits of Port1 into STATUS register Continuously puts the upper four bits of Port1 into STATUS register Send Port2 value to the system Only set/reset GateA20 line based on the system data bit 1 Send data back to the system as if it came from Keyboard Send data back to the system as if it came from Auxiliary Device Output next received byte of data from system to Auxiliary Device Reports the status of the test inputs Pulse only RC(the reset line) low for 6S if Command byte is even
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7.5
HARDWARE GATEA20/KEYBOARD RESET CONTROL LOGIC
The KBC implements a hardware control logic to speed-up GATEA20 and KBRESET. This control logic is controlled by LD5-CRF0 as follows: 7.5.1 KB Control Register (Logic Device 5, CR-F0) BIT NAME 7 KCLKS1 6 5 4 3 2 P92EN 1 HGA20 0 HKBRST
KCLKS0 Reserved Reserved Reserved
KCLKS1, KCLKS0 This 2 bits are for the KBC clock rate selection. = 0 0 KBC clock input is 6 Mhz = 0 1 KBC clock input is 8 Mhz = 1 0 KBC clock input is 12 Mhz = 1 1 KBC clock input is 16 Mhz P92EN (Port 92 Enable) A "1" on this bit enables Port 92 to control GATEA20 and KBRESET. A "0" on this bit disables Port 92 functions. HGA20 (Hardware GATE A20) A "1" on this bit selects hardware GATEA20 control logic to control GATE A20 signal. A "0" on this bit disables hardware GATEA20 control logic function. HKBRST (Hardware Keyboard Reset) A "1" on this bit selects hardware KB RESET control logic to control KBRESET signal. A "0" on this bit disables hardware KB RESET control logic function. When the KBC receives data that follows a "D1" command, the hardware control logic sets or clears GATE A20 according to the received data bit 1. Similarly, the hardware control logic sets or clears KBRESET depending on the received data bit 0. When the KBC receives a "FE" command, the KBRESET is pulse low for 6S(Min.) with 14S(Min.) delay. GATEA20 and KBRESET are controlled by either the software control or the hardware control logic and they are mutually exclusive. Then, GATEA20 and KBRESET are merged along with Port92 when P92EN bit is set. 7.5.2 Port 92 Control Register (Default Value = 0x24) BIT NAME 7 Res. (0) 6 Res. (0) 5 Res. (1) 4 Res. (0) 3 Res. (0) 2 Res. (1) 1 SGA20 0 PLKBRST
SGA20 (Special GATE A20 Control) A "1" on this bit drives GATE A20 signal to high. A "0" on this bit drives GATE A20 signal to low. PLKBRST (Pull-Low KBRESET) A "1" on this bit causes KBRESET to drive low for 6S(Min.) with 14S(Min.) delay. Before issuing another keyboard reset command, the bit must be cleared.
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PRELIMINARY
8. GENERAL PURPOSE I/O
W83977F/ AF provides 14 Input/Output ports that can be individually configured to perform a simple basic I/O function or a pre-defined alternate function. Those 14 GP I/O ports are divided into two groups, the first group contains 8 ports, and the other group contains only 6 ports. Each port in the first group corresponds to a configuration register in logical device 7. Each port in the second group corresponds to a configuration register in logical device 8. Users can select those I/O ports functions by independently programming the configuration registers. Figure 8.1 and 8.2 respectively show the GP I/O port's structure of logical device 7 and device 8. Right after Power-on reset, those ports perform basic I/O functions.
Figure 8.1
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Figure 8.2
8.1
Basic I/O functions
The Basic I/O functions of W83977F/ AF provide several I/O operations including driving a logic value to output port, latching a logic value from input port, inverting the input/output logic value, and steering Common Interrupt (only available in the second group of the GP I/O port). Common Interrupt is the ORed function of all interrupt channels in the second group of the GP I/O ports, and it also connects to a 1ms debounce filter which can reject a noise of 1 ms pulse width or less. There are two 8-bit registers, GP1 and GP2, which are directly connected to both groups of GP I/O ports. Each GP I/O port is represented as a bit in one of two 8-bit registers. Only 6 bits of GP2 are implemented. Table 11.1.1 shows their combinations of Basic I/O functions, and Table 11.1.2 shows the register bit assignments of GP1 and GP2.
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Table 8.1.1 I/O BIT 0 = OUTPUT 1 = INPUT 0 0 0 0 1 1 1 1 ENABLE INT BIT 0 = DISABLE 1 = ENABLE 0 0 1 1 0 0 1 1 POLARITY BIT 0 = NON INVERT 1 = INVERT 0 1 0 1 0 1 0 1 Basic non-inverting output Basic inverting output Non-inverted output bit value of GP2 drive to Common Interrupt Inverted output bit value of GP2 drive to Common Interrupt Basic non-inverting input Basic inverting input Non-inverted input drive to Common Interrupt Inverted input drive to Common Interrupt BASIC I/O OPERATIONS
Table 8.1.2 GP I/O PORT ACCESSED REGISTER REGISTER BIT ASSIGNMENT BIT 0 BIT 1 BIT 2 BIT 3 GP1 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 GP2 BIT 2 BIT 3 BIT 4 BIT 5 GP I/O PORT GP10 GP11 GP12 GP13 GP14 GP15 GP16 GP17 GP20 GP21 GP22 GP23 GP24 GP25
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8.2
Alternate I/O Functions
W83977F/ AF provides several alternate functions which are scattered among the GP I/O ports. Table 8.2.1 shows their assignments. Polarity bit can also be set to alter their polarity of alternate functions. Table 8.2.1 GP I/O PORT GP10 GP11 GP12 GP13 GP14 GP15 GP16 GP17 GP20 GP21 GP22 GP23 GP24 GP25 ALTERNATE FUNCTION Interrupt Steering Interrupt Steering Watching Dog Timer Output/IRRX input Power LED output/ IRTX output [W83977AF only] General Purpose Address Decoder/ Keyboard Inhibit(P17) General Purpose Write Strobe/ 8042 P12 Watching Dog Timer Output Power LED output Keyboard Reset (8042 P20) 8042 P13 8042 P14 8042 P15 8042 P16 GATE A20 (8042 P21)
8.2.1 Interrupt Steering GP10 and GP11 can be programmed to map their own interrupt channels. The selection of IRQ channel can be done in configure registers CR70 and CR72 of logical device 7. Each interrupt channel also has its own 1 ms debounce filter that is used to reject any noise which is equal to or less than 1 ms wide. 8.2.2 Watch Dog Timer Output Watch Dog Timer contains a one minutes resolution down counter, CRF2 of Logical Device 8, and two watch Dog control registers, WDT_CTRL0 and WDT_CTRL1 of Logical Device 8. The down counter can be programmed within the range from 1 to 255 minutes. Writing any new non-zero value to CRF2 or reset signal coming from a Mouse interrupt or Keyboard interrupt (CRF2 also contains non-zero value) will cause the Watch Dog Timer to reload and start to count down from the new value. As the counter reaches zero, (1) Watch Dog Timer time-out occurs and the bit 0 of WDT_CTRL1 will be set to logic 1; (2) Watch Dog interrupt output is asserted if the interrupt is enable in CR72 of logical device 8; and (3) Power LED starts to toggle output if the bit 3 of WDT_CTRL0 is enabled. WDT_CTRL1 also can be accessed through GP2 I/O base address + 1.
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8.2.3 Power LED The Power LED function provides 1 Hertz rate toggle pulse output with 50 percent duty cycle. Table 8.2.2 shows how to enable Power LED. Table 8.2.2 WDT_CTRL1 BIT[1] 1 0 0 0 WDT_CTRL0 BIT[3] X 0 1 1 WDT_CTRL1 BIT[0] X X 0 1 POWER LED STATE 1 Hertz Toggle pulse Continuous high or low * Continuous high or low * 1 Hertz Toggle pulse
* Note: Continuous high or low depends on the polarity bit of GP13 or GP17 configure registers.
8.2.4 General Purpose Address Decoder General Purpose Address Decoder provides two address decode as AEN equal to logic 0. The address base is stored at CR62, CR63 of logical device 7. The decode output is normally active low. Users can alter its polarity through the polarity bit of the GP14's configuration register. 8.2.5 General Purpose Write Strobe General Purpose Write Strobe is an address decoder that performs like General Purpose Address Decoder, but it has to be qualified by IOW and AEN. Its output is normally active low. Users can alter its polarity through the polarity bit of the GP15's configuration register.
9. PLUG AND PLAY CONFIGURATION
The W83977F/ AF provides many configuration registers for setting up different types of configurations. There are two approaches to entering the configuration state and accessing these configuration registers, Comply PnP and Compatible PnP. The Comply PnP protocol is based on the Plug and Play ISA Specification. The Compatible PnP protocol is similar to previous Winbond I/O's protocol. The Power-On-Setting upon the Pin 51 (DTRB ) decides the method of entering the configuration mode. In W83977F/ AF, there are nine Logical Devices (from Logical Device 0 to Logical Device 8) which correspond to nine individual functions: FDC, PRT, UART1, UART2, RTC, KBC, IR, GPIO1, GPIO2 in listed order. Each Logical Device has its own configuration registers (above CR30). Host can access those registers only after entering configuration mode.
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PRELIMINARY
9.1
Comply PnP
The protocol of Comply PnP is 100% compatible with the Plug and Play ISA Specification. W83977F/ AF provides built-in Plug and Play state machine to control the configuration flow. The state machine supports four states: Wait for Key state, Sleep state, Isolation state, and Configure State. According to Plug and Play ISA Specification, users can transit the four states by accessing the configuration registers, CR00 - CR07.
9.1.1 Wait for Key State All cards enter this state after power-up reset or in response to the Reset and Wait for Key commands. No command is active in this state until the initiation key is detected on the ISA bus. The initiation key is a sequence of 32 hexadecimal number which will be shifted into LFSR (linear feedback shift register) built in W83977F/ AF. The Wait for Key state is the default state for Plug and Play cards during normal system operation. After configuration and activation, software should return all cards to this state. 9.1.2 Sleep State In this state, Plug and Play wait for a Wake[CSN] command. This command will selectively enable one or more cards to enter either the Isolation or Configure states based on the write data and the value of the CSN on each card. If the write data for the Wake[CSN] command is zero then all cards that have not been assigned a CSN will enter the Isolation state. If the write data for the Wake[CSN] command is not zero then the one card whose assigned CSN matches the parameter of the Wake[CSN] command will enter the Configure state. 9.1.3 Isolation State In this state, Plug and Play cards respond to reads of the Serial Isolation registers according to Isolation protocol. An unique CSN is assigned after the card is isolated 9.1.4 Configure State A card in the Configure state responds to all configuration commands including reading the card's resource configure information and programming the card's resource selections. Only one card may be in this state at a time.
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PRELIMINARY
9.2
Compatible PnP
9.2.1 Extended Function Registers In Compatible PnP, there are two ways to enter Extended Function mode (which is same as Configure State in Comply PnP) and read or write the configuration registers. HEFRAS (CR26 bit 6) can be used to select one out of these two methods of entering the Extended Function mode as follows: HEFRAS 0 1 address and value write 87h to the location 3F0h twice write 87h to the location 370h twice
After Power-on reset, the value on RTSA (pin 43) is latched by HEFRAS of CR26. In Compatible PnP, a specific value (87h) must be written twice to the Extended Functions Enable Register (I/O port address 3F0h or 370h). Secondly, an index value (02h, 07h-FEh) must be written to the Extended Functions Index Register (I/O port address 3F0h or 370h same as Extended Functions Enable Register) to identify which configuration register is to be accessed. The designer can then access the desired configuration register through the Extended Functions Data Register (I/O port address 3F1h or 371h). After programming of the configuration register is finished, an additional value(AAh) should be written to EFERs to exit the Extended Function mode to prevent unintentional access to those configuration registers. The designer can also set bit 5 of CR26 (LOCKREG) to high to protect the configuration registers against accidental accesses. The configuration registers can be reset to their default or hardware settings only by a cold reset (pin MR = 1). A warm reset will not affect the configuration registers. 9.2.2 Extended Functions Enable Registers (EFERs) After a power-on reset, the W83977F/ AF enters the default operating mode. Before the W83977F/ AF enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers. On a PC/AT system, their port addresses are 3F0h or 370h (as described in previous section). 9.2.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs) After the extended function mode is entered, the Extended Function Index Register (EFIR) must be loaded with an index value (02h, 07h-FEh) to access Configuration Register 0 (CR0), Configuration Register 7 (CR07) to Configuration Register FE (CRFE), and so forth through the Extended Function Data Register (EFDR). The EFIRs are write-only registers with port address 3F0h or 370h (as described in section 12.2.1) on PC/AT systems; the EFDRs are read/write registers with port address 3F1h or 371h (as described in section 9.2.1) on PC/AT systems.
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10. CONFIGURATION REGISTER
10.1 Chip (Global) Control Register
CR00 (only available in comply PnP mode) Bit 7-0 : IORDPRA9 - IORDPRA2 --> Set RD_DATA Port A9-A2 CR01 (only available in comply PnP mode) Bit7-0 : SISO 7-0 --> Serial Isolation CR02 (Default 0x00) Bit 7-3 : Reserved. Bit 2: RSTCSN --> Reset CSN to 0. Only available in comply PnP mode. Bit 1: RTUWAIT -- > Return to Wait for Key state. Only available in comply PnP mode. Bit 0 : SWRST --> Soft Reset. CR03 (only available in comply PnP mode) Bit 7-0 : WAKCSN7 - WAKCSN0 --> Wake CSN CR04 (only available in comply PnP mode) Bit 7-0 : RSODAT7 - RSODAT 0 --> Resource Data CR05 (only available in comply PnP mode) Bit 7-1 : Reserved Bit 0 : RSOSTAT -- > resource status bit CR06 (only available in comply PnP mode) Bit 7-0 : CSN7 -CSN0 --> Card Select Number 7 - 0 CR07 Bit 7-0 : LDNB7 - LDNB0 --> Logical Device Number Bit 7 - 0 CR20 Bit 7-0 : DEVIDB7 - DEBIDB0 -- > Device ID Bit 7 - Bit 0 = 0x97 (read only). CR21 Bit 7-0 : DEVREVB7 - DEBREVB0 -- > Device Rev Bit 7 - Bit 0 = 0x71 (read only). CR22 (Default 0xff) Bit 7-6 : Reserved. Bit 5 : URBPWD = 0 Power down = 1 No Power down Bit 4 : URAPWD = 0 Power down = 1 No Power down
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Bit 3 : PRTPWD = 0 Power down = 1 No Power down Bit 2 : IRPWD = 0 Power down = 1 No Power down Bit 1 : Reserved. Bit 0 : FDCPWD = 0 Power down = 1 No Power down CR23 (Default 0x00) Bit7-6 : Reserved Bit 5-3 : APDTMS2 APDTMS1 APDTMS0 = 000 4 seconds count-down time of the APD mode. = 001 8 seconds count-down time of the APD mode. = 010 16 seconds count-down time of the APD mode. = 011 32 seconds count-down time of the APD mode. = 100 1 minute count-down time of the APD mode. = 101 2 minutes count-down time of the APD mode. = 110 4 minutes count-down time of the APD mode. = 111 16 minutes count-down time of the APD mode. Bit 2-0 : OSCS2, OSCS1, OSCS0. = 000 Default power-on state after power on reset. = 1xx Stop Clock supply to whole chip, but PLL circuit still in operation. = 001 Stop Clock supply to whole chip and PLL circuit. = 010 Standby for automatic power-down(APD). = 011 Automatic power-down(APD) has been happened. CR24 (Default 0b1ss00sss) Bit 7 : EN16SA = 0 12 bit Address Qualification = 1 16 bit Address Qualification Bit 6-5 : CLKSEL, ENPLL = 00 The clock input on Pin 1 should be 14.31818 Mhz. = 01 The clock input on Pin 1 should be 24 Mhz. = 11 The clock input on Pin 1 should be 48 Mhz. Bit 4 : RWPNPREG = 0 Disable read/write PnP mode config registers by using the method of non-PnP mode = 1 Enable read/write PnP mode config registers by using the method of non-PnP mode Bit 3 : Reserved
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Bit 2 : ENKBRTC = 0 KBC and RTC are disabled after hardware reset. = 1 KBC and RTC are active after hardware reset. This bit is read only, and set/reset by hardware setting. Bit 1 : ENPNP = 0 Disable Comply PnP = 1 Enable Comply PnP Bit 0 : PNPCSV = 0 The Compatible and Comply PnP has default value = 1 The Compatible and Comply PnP has no default value CR25 (Default 0x00) Bit 7-6 : Reserved Bit 5 : URBTRI Bit 4 : URATRI Bit 3 : PRTTRI Bit 2 : IRTRI [W83977AF only] Bit 1 : Reserved. Bit 0 : FDCTRI. CR26 (Default 0b0s000000) Bit 7 : SEL4FDD = 0 Select two FDD mode. = 1 Select four FDD mode. Bit 6 : HEFRAS These two bits define how to enable Configuration mode. HEFRAS Address and Value = 0 Write 87h to the location 3F0h twice. = 1 Write 87h to the location 370h twice. Bit 5 : LOCKREG = 0 Enable R/W Configuration Registers. = 1 Disable R/W Configuration Registers. Bit 4 : DSIRLGRQ [W83977AF only] = 0 Enable IR legacy mode on IRQ and DRQ selection, then MCR register bit 3 is effective in selecting IRQ and DRQ. = 1 Disable IR legacy mode on IRQ and DRQ selection, then MCR register bit 3 is not effective in selecting IRQ and DRQ. Bit 3 : DSFDLGRQ = 0 Enable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is effective in selecting IRQ = 1 Disable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is not effective in selecting IRQ
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Bit 2 : DSPRLGRQ = 0 Enable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is effective on selecting IRQ = 1 Disable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is not effective on selecting IRQ Bit 1 : DSUALGRQ = 0 Enable UART A legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ = 1 Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ Bit 0 : DSUBLGRQ = 0 Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ = 1 Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ CR28 (Default 0x00) Bit 7-5: Reserved. Bit 4 : IRQ Sharing selection. =0 Disable IRQ Sharing =1 Enable IRQ Sharing Bit 3 :Reserved Bit 2-0 : PRTMODS2 - PRTMODS0 = 0xx Parallel Port Mode = 100 Reserved = 101 External FDC Mode = 110 Reserved = 111 External two FDC Mode CR29 [W83977AF only] Bit 7-0 : CPSIDB7 - CPSIDB0 --> Comply PnP Serial ID Bit 7 - Bit 0. CR2A (Default 0x00) Bit 7 : PIN57S = 0 KBRST = 1 GP12 Bit 6 : PIN56S = 0 GA20 = 1 GP11 Bit 5-4 : PIN40S1, PIN40S0 = 00 CIRRX [W83977AF only] = 01 GP24 = 10 8042 P13 = 11 Reserved
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Bit 3-2 : PIN39S1, PIN39S0 = 00 IRRXH [W83977AF only] = 01 IRSL0 [W83977AF only] = 10 GP25 = 11 CTSC [W83977AF only] Bit 1-0 : PIN3S1, PIN3S0 = 00 DRVDEN1 = 01 GP10 = 10 8042 P12 = 11 nDSRC CR2B (Default 0x00) Bit 7-6 : PIN73S1, PIN73S0 = 00 PANSW = 01 GP23 = 10 Reserved = 11 DCDC [W83977AF only] Bit 5 : PIN72S =0 PSCTRL = 1 GP22 Bit 4-3 : PIN70S1, PIN70S0 = 00 SMI = 01 GP21 = 10 8042 P16 = 11 RIC [W83977AF only] Bit 2-1 : PIN69S1, PIN69S0 = 00 PHRI = 01 GP20 = 10 Reserved = 11 Reserved Bit 0 : PIN58S = 0 KBLOCK = 1 GP13 CR2C (Default 0x00) Bit 7-6 : PIN121S1, PIN121S0 = 00 DRQ0 = 01 GP17 = 10 8042 P14 = 11 nDTRC [W83977AF only]
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Bit 5-4 : PIN119S1, PIN119S0 = 00 NDACK0 = 01 GP16 = 10 8042 P15 = 11 nRTSC Bit 3-2 : PIN104S1, PIN104S0 = 00 IRQ15 = 01 GP15 = 10 WDTO = 11 IRSL2 [W83977AF only] Bit 1-0 : PIN103S1, PIN103S0 = 00 IRQ14 = 01 GP14 = 10 PLEDO = 11 IRSL1 [W83977AF only] CR2D (Default 0x00) Test Modes: Reserved for Winbond. CR2E (Default 0x00) Test Modes: Reserved for Winbond. CR2F (Default 0x00) Test Modes: Reserved for Winbond.
10.2 Logical Device 0 (FDC)
CR30 (Default 0x01) Bit 7-1 : Reserved. Bit 0 : = 1 Activates the logical device. = 0 Logical device is inactive. CR31 Bit 7-2 : Reserved. Bit 1 : ENRNGCK -- > Enable I/O Range check Bit 0 : FORIORD --> Forces LDN to respond I/O read CR60, CR 61 (Default 0x03, 0xf0) These two registers select FDC I/O base address [0x100:0xFF8] on 8 byte boundaries. CR70 (Default 0x06) Bit 7-4 : Reserved. Bit 3-0 : These bits select IRQ resource for FDC.
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CR71 (Default 0x02, read only) Bit 7-2 : Reserved. Bit 1 : IRQLEV -- > IRQ Level = 1: High; = 0: Low Bit 0 : IRQTYPE --> IRQ Type = 1: Level trigger; = 0: Edge trigger CR74 (Default 0x02) Bit 7-3 : Reserved. Bit 2-0 : These bits select DRQ resource for FDC. = 0x00 DMA0 = 0x01 DMA1 = 0x02 DMA2 = 0x03 DMA3 = 0x04-0x07 No DMA active CRF0 (Default 0x0E) FDD Mode Register Bit 7 : FIPURDWN This bit controls the internal pull-up resistors of the FDC input pins RDATA, INDEX, TRAK0, DSKCHG, and WP. = 0 The internal pull-up resistors of FDC are turned on.(Default) = 1 The internal pull-up resistors of FDC are turned off. Bit 6 : INTVERTZ This bit determines the polarity of all FDD interface signals. = 0 FDD interface signals are active low. = 1 FDD interface signals are active high. Bit 5 : DRV2EN (PS2 mode only) When this bit is a logic 0, indicates a second drive is installed and is reflected in status register A. Bit 4 : Swap Drive 0, 1 Mode = 0 No Swap (Default) = 1 Drive and Motor sel 0 and 1 are swapped. Bit 3-2 Interface Mode = 11 AT Mode (Default) = 10 (Reserved) = 01 PS/2 = 00 Model 30 Bit 1 : FDC DMA Mode = 0 Burst Mode is enabled = 1 Non-Burst Mode (Default) Bit 0 : Floppy Mode = 0 Normal Floppy Mode (Default) = 1 Enhanced 3-Mode FDD
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CRF1 (Default 0x00) Bit 7-6 : Boot Floppy = 00 FDD A = 01 FDD B = 10 FDD C = 11 FDD D Bit 5 : Media ID1 Polarity = 0 Non-Inverse = 1 Inverse Bit 4 : Media ID0 Polarity = 0 Non-Inverse = 1 Inverse Bit 3-2 : Density Select = 00 Normal (Default) = 01 Normal = 10 1 ( Forced to logic 1) = 11 0 ( Forced to logic 0) Bit 1 : DISFDDWR = 0 Enable FDD write. = 1 Disable FDD write(forces pins WE, WD to stay high). Bit 0 : SWWP = 0 Normal, use WP to determine whether the FDD is write protected or not. = 1 FDD is always write-protected. CRF2 (Default 0xFF) Bit 7-6 : FDD D Drive Type Bit 5-4 : FDD C Drive Type Bit 3-2 : FDD B Drive Type Bit 1:0 : FDD A Drive Type When FDD is in enhanced 3-mode(CRF0.bit0=1),these bits determine SELDEN value in TABLE A of CRF4 and CRF5 as follows. DTYPE1 0 0 0 0 0 1 1 DPYTE0 0 0 0 0 1 0 1 DRATE1 1 0 0 1 X X 0 DRATE0 1 0 1 0 X X 1 SELDEN 1 1 0 0 0 1 0
Note: X means don't care.
CRF4 (Default 0x00) FDD0 Selection: Bit 7 : Reserved. Bit 6 : Precomp. Disable. = 1 Disable FDC Precompensation. = 0 Enable FDC Precompensation. Bit 5 : Reserved.
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Bit 4-3 : DRTS1, DRTS0 : Data Rate Table select (Refer to TABLE A). = 00 Select Regular drives and 2.88 format = 01 Specifical application = 10 2 Meg Tape = 11 Reserved Bit 2 : Reserved. Bit 1:0 : DMOD0, DMOD1 : Drive Model select (Refer to TABLE B). CRF5 (Default 0x00) FDD1 Selection : Same as FDD0 of CRF4. TABLE A Drive Rate Table Select DRTS1 0 DRTS0 0 1 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1 Data Rate DRATE1 DRATE0 1 0 1 0 1 0 1 0 1 0 1 0 Selected Data Rate MFM 1Meg 500K 300K 250K 1Meg 500K 500K 250K 1Meg 500K 2Meg 250K FM --250K 150K 125K --250K 250K 125K --250K --125K SELDEN CRF0 bit 0=0 1 1 0 0 1 1 0 0 1 1 0 0
Note:Refer to CRF2 for SELDEN value in the cases when CRF0, bit0=1.
TABLE B DMOD0 0 DMOD1 0 DRVDEN0(pin 2) SELDEN DRVDEN1(pin 3) DRATE0 DRIVE TYPE 4/2/1 MB 3.5 2/1 MB 5.25 2/1.6/1 MB 3.5 (3-MODE)
0 1 1
1 0 1
DRATE1 SELDEN DRATE0
DRATE0 DRATE0 DRATE1
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10.3 Logical Device 1 (Parallel Port)
CR30 (Default 0x01 when PNPCSV=0 at POR) Bit 7-1 : Reserved. Bit 0 : = 1 Activates the logical device. = 0 Logical device is inactive. CR31 Bit 7-2 : Reserved. Bit 1 : ENRNGCK -- > Enable I/O Range check Bit 0 : FORIORD --> Forces LDN to respond I/O read CR60, CR 61 (Default 0x03, 0x78 at PNPCSV=0) These two registers select Parallel Port I/O base address. [0x100:0xFFC] on 4 byte boundaries(EPP not supported) or [0x100:0xFF8] on 8 byte boundaries(all modes supported, EPP is only available when the base address is on an 8byte boundary). CR70 (Default 0x07 when PNPCSV=0 at POR) Bit 7-4 : Reserved. Bit [3:0] : These bits select IRQ resource for Parallel Port. CR71 (Default 0x02, read only) Bit 7-2 : Reserved. Bit 1 : IRQLEV -- > IRQ Level = 1: High; = 0: Low Bit 0 : IRQTYPE --> IRQ Type = 1: Level trigger; = 0: Edge trigger
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CR74 (Default 0x04) Bit 7-3 : Reserved. Bit 2-0 : These bits select DRQ resource for Parallel Port. 0x00=DMA0 0x01=DMA1 0x02=DMA2 0x03=DMA3 0x04-0x07= No DMA active CRF0 (Default 0x3F) Bit 7 : PP Interrupt Type: Not valid when the parallel port is in the printer Mode (100) or the standard & Bi-directional Mode (000). =1 =0 Pulsed Low, released to high-Z . IRQ follows nACK when parallel port in EPP Mode or [Printer, SPP, EPP] under ECP.
Bit [6:3] : ECP FIFO Threshold. Bit 2-0 Parallel Port Mode (CR F1 PRTMODS2= logical 1) = 100 Printer Mode (Default) = 000 Standard and Bi-direction (SPP) mode = 001 EPP-1.9 and SPP mode = 101 EPP-1.7 and SPP mode = 010 ECP mode = 011 ECP and EPP-1.9 mode = 111 ECP and EPP-1.7 mode.
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10.4 Logical Device 2 (UART A))
CR30 (Default 0x01 when PNPCSV=0 at POR) Bit 7-1 : Reserved. Bit 0 : = 1 Activates the logical device. = 0 Logical device is inactive. CR31 Bit 7-2 : Reserved. Bit 1 : ENRNGCK -- > Enable I/O Range check Bit 0 : FORIORD --> Forces LDN to respond I/O read CR60, CR 61 (Default 0x03, 0xF8 when PNPCSV=0 at POR ) These two registers select Serial Port 1 I/O base address [0x100:0xFF8] on 8 byte boundaries. CR70 (Default 0x04 when PNPCSV=0 at POR) Bit 7-4 : Reserved. Bit [3:0] : These bits select IRQ resource for Serial Port 1. CR71(Default 0x02, read only) Bit 7-2 : Reserved. Bit 1 : IRQLEV -- > IRQ Level = 1: High; = 0: Low Bit 0 : IRQTYPE --> IRQ Type = 1: Level trigger; = 0: Edge trigger CRF0 (Default 0x00) Bit 7-2 : Reserved. Bit 1-0 : SUACLKB1, SUACLKB0 = 00 = 01 = 10 = 11 UART A clock source is 1.8462 Mhz (24MHz/13) UART A clock source is 2 Mhz (24MHz/12) UART A clock source is 24 Mhz (24MHz/1) UART A clock source is 14.769 Mhz (24MHz/1.625)
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10.5 Logical Device 3 (UART B)
CR30 (Default 0x01 when PNPCSV=0 at POR) Bit 7-1 : Reserved. Bit 0 : = 1 Activates the logical device. = 0 Logical device is inactive. CR31 Bit 7-2 : Reserved. Bit 1 : ENRNGCK -- > Enable I/O Range check Bit 0 : FORIORD --> Forces LDN to respond I/O read CR60, CR 61 (Default 0x02, 0xF8 when PNPCSV=0 at POR) These two registers select Serial Port 2 I/O base address [0x100:0xFF8] on 8 byte boundaries. CR70 (Default 0x03 when PNPCSV=0 at POR) Bit 7-4 : Reserved. Bit [3:0] : These bits select IRQ resource for Serial Port 2. CR71 (Default 0x02, read only) Bit 7-2 : Reserved. Bit 1 : IRQLEV -- > IRQ Level = 1: High; = 0: Low Bit 0 : IRQTYPE --> IRQ Type = 1: Level trigger; 0: Edge trigger CRF0 (Default 0x00) Bit 7-2 : Reserved. Bit 1-0 : SUBCLKB1, SUBCLKB0 = 00 = 01 = 10 = 11 UART B clock source is 1.8462 Mhz (24MHz/13) UART B clock source is 2 Mhz (24MHz/12) UART B clock source is 24 Mhz (24MHz/1) UART B clock source is 14.769 Mhz (24MHz/1.625)
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10.6 Logical Device 4 (Real Time Clock)
CR30 (Default 0x01 when PENKRC=1 at POR) Bit 7-1 : Reserved. Bit 0 : = 1 Activates the logical device. = 0 Logical device is inactive. CR31 Bit 7-2 : Reserved. Bit 1 : ENRNGCK -- > Enable I/O Range check Bit 0 : FORIORD --> Forces LDN to respond I/O read CR60, CR 61 (Default 0x00, 0x70 when PENKRC=1 at POR) These two registers select Real Time Clock I/O base address [0x100:0xFFE] on 2 byte boundaries. CR70 (Default 0x08 when PENKRC=1 at POR) Bit 7-4 : Reserved. Bit [3:0] : These bits select IRQ resource for RTC. CR71 (Default 0x00, read/write) Bit 7-2 : Reserved. Bit 1 : IRQLEV -- > IRQ Level = 1: High; = 0: Low Bit 0 : IRQTYPE --> IRQ Type = 1: Level trigger; = 0: Edge trigger CRF0 (Default 0x00) RTC Mode Register Bit 7-6 : = 00 Select BANK0 of RAM = 01 Select BANK1 of RAM = 10 Select BANK2 of RAM Bit 5-4 : Reserved. Bit 3 : = 1 Lock CMOS RAM E0-FFh Bit 2 : = 1 Lock CMOS RAM C0-DFh Bit 1 : = 1 Lock CMOS RAM A0-BFh Bit 0 : = 1 Lock CMOS RAM 80-9Fh
Note : Once set, bit[3:0] can not be cleared by a write; bit[3:0] is cleared only on Power-On Reset or upon a Hard Reset.
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10.7 Logical Device 5 (KBC)
CR30 (Default 0x01 when PENKRC=1 at POR) Bit 7-1 : Reserved. Bit 0 : = 1 Activates the logical device. = 0 Logical device is inactive. CR31 Bit 7-2 : Reserved. Bit 1 : ENRNGCK -- > Enables I/O Range check Bit 0 : FORIORD --> Forces LDN to respond I/O read CR60, CR 61 (Default 0x00, 0x60 when PENKRC=1 at POR) These two registers select the first KBC I/O base address [0x100:0xFFF] on 1 byte boundaries. CR62, CR 63 (Default 0x00, 0x64 when PENKRC=1 at POR) These two registers select the second KBC I/O base address [0x100:0xFFF] on 1 byte boundaries. CR70 (Default 0x01 when PENKRC=1 at POR) Bit 7-4 : Reserved. Bit [3:0] : These bits select IRQ resource for KINT(keyboard). CR71 (Default 0x02, Read only) Bit 7-2 : Reserved. Bit 1 : IRQLEV -- > IRQ Level = 1: High; = 0: Low Bit 0 : IRQTYPE --> IRQ Type = 1: Level trigger; = 0: Edge trigger CR72 (Default 0x0C when PENKRC=1 at POR) Bit 7-4 : Reserved. Bit [3:0] : These bits select IRQ resource for MINT(PS2 Mouse) CR73 (Default 0x02) Bit 7-2 : Reserved. Bit 1 : IRQLEV -- > IRQ Level = 1: High; = 0: Low Bit 0 : IRQTYPE --> IRQ Type = 1: Level trigger; = 0: Edge trigger
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CRF0 (Default 0x40) Bit 7-6 : KBC clock rate selection = 00 Select 6MHz as KBC clock input. = 01 Select 8MHz as KBC clock input. = 10 Select 12Mhz as KBC clock input. = 11 Select 16Mhz as KBC clock input. Bit 5-3 : Reserved. Bit 2 : = 0 Port 92 disable. = 1 Port 92 enable. Bit 1 : = 0 Gate20 software control. = 1 Gate20 hardware speed up. Bit 0 : = 0 KBRST software control. = 1 KBRST hardware speed up.
10.8 Logical Device 6 (IR)
CR30 (Default 0x00) Bit 7-1 : Reserved. Bit 0 : = 1 Activates the logical device. = 0 Logical device is inactive. CR31 Bit 7-2 : Reserved. Bit 1 : ENRNGCK -- > Enable I/O Range check Bit 0 : FORIORD --> Forces LDN to respond I/O read CR60, CR 61 (Default 0x00, 0x00) These two registers select IR I/O base address [0x100:0xFF8] on 8 byte boundaries. CR70 (Default 0x00) Bit 7-4 : Reserved. Bit [3:0] : These bits select IRQ resource for IR. CR71 (Default 0x02, read only) Bit 7-2 : Reserved. Bit 1 : IRQLEV -- > IRQ Level = 1: High; = 0: Low Bit 0 : IRQTYPE --> IRQ Type = 1: Level trigger; = 0: Edge trigger
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CR74 (Default 0x04) Bit 7-3 : Reserved. Bit 2-0 : These bits select DRQ resource for RX of UART C. = 0x00 DMA0 = 0x01 DMA1 = 0x02 DMA2 = 0x03 DMA3 = 0x04-0x07 No DMA active CR75 (Default 0x04) Bit 7-3 : Reserved. Bit 2-0 : These bits select DRQ resource for TX of UART C. = 0x00 DMA0 = 0x01 DMA1 = 0x02 DMA2 = 0x03 DMA3 = 0x04-0x07 No DMA active CRF0 (Default 0x00) Bit 7-4 : Reserved. Bit 3 : RXW4C =0 No reception delay when SIR is changed from TX mode to RX mode. = 1 Reception delays 4 characters-time(40 bit-time) when SIR is changed from TX mode to RX mode. Bit 2 : TXW4C =0 mode No transmission delay when SIR is changed from RX mode to TX mode. = 1 Transmission delays 4 characters-time(40 bit-time) when SIR is changed from RX to TX mode. =0 =1 =0 =1 No append hardware CRC value as data in FIR/MIR mode. Append hardware CRC value as data in FIR/MIR mode. Disable IR Bank selection. Enable IR Bank selection.
Bit 1 : APEDCRC
Bit 0 : ENBNKSEL; Bank select enable
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10.9 Logical Device 7 (Auxiliary I/O Part I)
CR30 (Default 0x00) Bit 7-1 : Reserved. Bit 0 : = 1 Activates the logical device. = 0 Logical device is inactive. CR31 Bit 7-2 : Reserved. Bit 1 : ENRNGCK -- > Enable I/O Range check Bit 0 : FORIORD --> Forces LDN to respond I/O read CR60, CR 61 (Default 0x00, 0x00) These two registers select GP1 I/O base address [0x100:0xFFF] on 1 byte boundaries. CR62, CR 63 (Default 0x00, 0x00) These two registers select GP14 alternate function Primary I/O base address [0x100:0xFFE] on 2 byte boundaries; They are available as you setting GP14 to be an alternate function (General Purpose Address Decode). CR64, CR 65 (Default 0x00, 0x00) These two registers select GP15 alternate function Primary I/O base address [0x100:0xFFF] on 1 byte boundaries; They are available as you setting GP15 to be an alternate function (General Purpose Write Decode). CR70 (Default 0x00) Bit 7-4 : Reserved. Bit 3-0 : These bits select IRQ resource for GP10 as you setting GP10 to be an alternate function (Interrupt Steering). CR71 (Default 0x02, read only) Bit 7-2 : Reserved. Bit 1 : IRQLEV -- > IRQ Level = 1: High; = 0: Low Bit 0 : IRQTYPE --> IRQ Type = 1: Level trigger; = 0: Edge trigger CR72 (Default 0x00) Bit 7-4 : Reserved. Bit 3-0 : These bits select IRQ resource for GP11 as you setting GP10 to be an alternate function (Interrupt Steering). CR73 (Default 0x02) Bit 7-2 : Reserved. Bit 1 : IRQLEV -- > IRQ Level = 1: High; = 0: Low Bit 0 : IRQTYPE --> IRQ Type = 1: Level trigger; = 0: Edge trigger
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CRE0 (GP10, Default 0x01) Bit 7-5 : Reserved. Bit 4 : IRQ Filter Select = 1 Debounce Filter Enabled = 0 Debounce Filter Bypassed Bit 3 : Select Function. = 1 Select Alternate Function : Interrupt Steering. = 0 Select Basic I/O Function. Bit 2 : Reserved. Bit 1 : Polarity. = 1 Invert. = 0 No Invert. Bit 0 : In/Out selection. = 1 Input. = 0 Output. CRE1 (GP11, Default 0x01) Bit 7-5 : Reserved. Bit 4 : IRQ Filter Select = 1 Debounce Filter Enabled = 0 Debounce Filter Bypassed Bit 3 : Select Function. = 1 Select Alternate Function : Interrupt Steering. = 0 Select Basic I/O Function. Bit 2 : Reserved. Bit 1 : Polarity. = 1 Invert. = 0 No Invert. Bit 0 : In/Out selection. = 1 Input. = 0 Output. CRE2 (GP12, Default 0x01) Bit 7-5 : Reserved Bit 4-3 : Select Function. = 00 Select Basic I/O function. = 01 Select 1st alternate function : Watching Dog Timer Output. = 10 Reserved = 11 Reserved Bit 2 : Reserved. Bit 1 : Polarity : 1 : Invert, 0 : No Invert Bit 0 : In/Out : 1 : Input, 0 : Output
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CRE3 (GP13, Default 0x01) Bit 7-5 : Reserved. Bit 4-3 : Select Function. = 00 Select Basic I/O function. = 01 Select 1st alternate function : Power LED output. = 10 Reserved = 11 Reserved Bit 2 : Reserved. Bit 1 : Polarity : 1 : Invert, 0 : No Invert Bit 0 : In/Out : 1 : Input, 0 : Output CRE4 (GP14, Default 0x01) Bit 7-5 : Reserved. Bit 4-3 : Select Function. = 00 Select Basic I/O function. = 01 Select 1st alternate function : General Purpose Address Decoder(Active Low when Bit 1 = 0, Decode two byte address). = 10 Select 2nd alternate function : Keyboard Inhibit(P17). = 11 Reserved Bit 2 : Reserved. Bit 1 : Polarity : 1 : Invert, 0 : No Invert Bit 0 : In/Out : 1 : Input, 0 : Output CRE5 (GP15, Default 0x01) Bit 7-5 : Reserved. Bit 4-3 : Select Function. = 00 Select Basic I/O function. = 01 General Purpose Write Strobe(Active Low when Bit 1 = 0). = 10 8042 P12. = 11 Reserved Bit 2 : Reserved. Bit 1 : Polarity : 1 : Invert, 0 : No Invert Bit 0 : In/Out : 1 : Input, 0 : Output CRE6 (GP16, Default 0x01) Bit 7-5 : Reserved. Bit 4-3 : Select Function. = 00 Select Basic I/O function. = 01 Select 1st alternate function : Watching Dog Timer Output. = 1x Reserved Bit 2 : Reserved. Bit 1 : Polarity : 1 : Invert, 0 : No Invert Bit 0 : In/Out : 1 : Input, 0 : Output
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CRE7 (GP17, Default 0x01) Bit 7-4 : Reserved. Bit 4-3 : Select Function. = 00 Select Basic I/O function. = 01 Select 1st alternate function : Power LED output. Please refer to TABLE C = 1x Reserved Bit 2 : Reserved. Bit 1 : Polarity : 1 : Invert, 0 : No Invert Bit 0 : In/Out : 1 : Input, 0 : Output TABLE C WDT_CTRL1* BIT[1]* 1 0 0 0 WDT_CTRL0* BIT[3] X 0 1 1 WDT_CTRL1 BIT[0] X X 0 1 POWER LED STATE 1 Hertz Toggle pulse Continuous high or low* Continuous high or low* 1 Hertz Toggle pulse
*Note: 1). Regarding to the contents of WDT_CTR1 and WDT_CTRL0, please refer to CRF3 and CRF4 in Logic Device 8. 2). Continuous high or low depends on the polarity bit of GP13 or GP17 configure registers.
CRF1 ( Default 0x00) General Purpose Read/Write Enable* Bit 7-2 : Reserved Bit 1 : = 1 Enable General Purpose Write Strobe = 0 Disable General Purpose Write Strobe Bit 0 : = 1 Enable General Purpose Address Decode = 0 Disable General Purpose Address Decode
*Note : If the logical device s activate bit is not set then bit 0 and 1 have no effect.
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10.10
Logical Device 8 (Auxiliary I/O Part II)
CR30 (Default 0x00) Bit 7-1 : Reserved. Bit 0 : = 1 Activates the logical device. = 0 Logical device is inactive. CR31 Bit 7-2 : Reserved. Bit 1 : ENRNGCK -- > Enable I/O Range check Bit 0 : FORIORD --> Forces LDN to respond I/O read CR60, CR 61 (Default 0x00, 0x00) These two registers select GP2 & Watch Dog I/O base address [0x100:0xFFE] on 2 byte boundaries. I/O base address + 1 : Watch Dog I/O base address. CR70 (Default 0x00) Bit 7-4 : Reserved. Bit 3-0 : These bits select IRQ resource for Common IRQ of GP20~GP25 at Logic Device 9. CR71 (Default 0x02) Bit 7-2 : Reserved. Bit 1 : IRQLEV -- > IRQ Level = 1: High; = 0: Low Bit 0 : IRQTYPE --> IRQ Type = 1: Level trigger; 0: Edge trigger CR72 (Default 0x00) Bit 7-4 : Reserved. Bit 3-0 : These bits select IRQ resource for Watch Dog. CR73 Bit 7-2 : Reserved. Bit 1 : IRQLEV -- > IRQ Level = 1: High; = 0: Low Bit 0 : IRQTYPE --> IRQ Type = 1: Level trigger; = 0: Edge trigger CRE8 (GP20, Default 0x01) Bit 7-5 : Reserved. Bit 4-3 : Select Function. = 00 Select basic I/O function = 01 Reserved = 10 Select alternate function : Keyboard Reset (connected to KBC P20) = 11 Reserved Bit 2 : Int En = 1 Enable Common IRQ = 0 Disable Common IRQ Bit 1 : Polarity : 1 : Invert, 0 : No Invert Bit 0 : In/Out : 1 : Input, 0 : Output
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CRE9 (GP21, Default 0x01) Bit 7-5 : Reserved Bit 4-3 : Select Function. = 00 Select Basic I/O function = 01 Reserved = 10 Select 2nd alternate function : Keyboard P13 I/O = 11 Reserved Bit 2 : Int En = 1 Enable Common IRQ = 0 Disable Common IRQ Bit 1 : Polarity : 1 : Invert, 0 : No Invert Bit 0 : In/Out : 1 : Input, 0 : Output CREA (GP22, Default 0x01) Bit 7-5 : Reserved. Bit 4-3 : Select Function. = 00 Select Basic I/O function. = 01 Reserved = 10 Select 2nd alternate function : Keyboard P14 I/O. = 11 Reserved Bit 2 : Int En =1 =0 Enable Common IRQ Disable Common IRQ
Bit 1 : Polarity : 1 : Invert, 0 : No Invert Bit 0 : In/Out : 1 : Input, 0 : Output@@ CREB (GP23, Default 0x01) Bit 7-5 : Reserved. Bit 4-3 : Select Function. = 00 Select Basic I/O function = 01 Reserved = 10 Select 2nd alternate function : Keyboard P15 I/O = 11 Reserved Bit 2 : Int En =1 =0 Enable Common IRQ Disable Common IRQ
Bit 1 : Polarity : 1 : Invert, 0 : No Invert Bit 0 : In/Out : 1 : Input, 0 : Output@
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CREC (GP24, Default 0x01) Bit 7-5 : Reserved. Bit 4-3 : Select Function. = 00 Select Basic I/O function = 01 Reserved = 10 Select 2nd alternate function : Keyboard P16 I/O = 11 Reserved Bit 2 : Int En =1 =0 Enable Common IRQ Disable Common IRQ
Bit 1 : Polarity : 1 : Invert, 0 : No Invert Bit 0 : In/Out : 1 : Input, 0 : Output CRED (GP25, Default 0x01) Bit 7-4 : Reserved. Bit 3 : Select Function. = 1 Select alternate function: GATE A20(Connect to KBC P21). = 0 Select basic I/O function Bit 2 : Int En =1 =0 Enable Common IRQ Disable Common IRQ
Bit 1 : Polarity : 1 : Invert, 0 : No Invert Bit 0 : In/Out : 1 : Input, 0 : Output CRF0 (Default 0x00) Debounce Filter Enable or Disable for General Purpose I/O Combined Interrupt. The Debounce Filter can reject a pulse with 1ms width or less. Bit 7-4 : Reserved Bit 3 : GP Common IRQ Filter Select = 1 Debounce Filter Enabled = 0 Debounce Filter Bypassed Bit 2-0 : Reserved CRF1 (Reserved)
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CRF2 (Default 0x00) Watching Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to load the value to Watching Dog Counter and start to count down. If the Bit2 and Bit 1 are set, any Mouse Interrupt or Keyboard Interrupt happen will also cause to reload the non-zero value to Watching Dog Counter and count down. Read this register can not access Watching Dog Timer Time-out value, but can access the current value in Watching Dog Counter. Bit 7-0 : = 0x00 Time-out Disable = 0x01 Time-out occurs after 1 minute = 0x02 Time-out occurs after 2 minutes = 0x03 Time-out occurs after 3 minutes ................................................ = 0xFF Time-out occurs after 255 minutes CRF3 (WDT_CTRL0, Default 0x00) Watching Dog Timer Control Register #0 Bit 7-4 : Reserved Bit 3 : When Time-out occurs, Enable or Disable Power LED with 1 Hz and 50% duty cycle output. = 1 Enable = 0 Disable Bit 2 : Mouse interrupt reset Enable or Disable = 1 Watching Dog Timer is reset upon a Mouse interrupt = 0 Watching Dog Timer is not affected by Mouse interrupt Bit 1 : Keyboard interrupt reset Enable or Disable = 1 Watching Dog Timer is reset upon a Keyboard interrupt = 0 Watching Dog Timer is not affected by Keyboard interrupt Bit 0 : Reserved. CRF4 (WDT_CTRL1, Default 0x00) Watching Dog Timer Control Register #1 Bit 7-4 : Reserved Bit 3 : Enable the rising edge of Keyboard Reset(P20) to force Time-out event, R/W* = 1 Enable = 0 Disable Bit 2 : Force Watching Dog Timer Time-out, Write only* = 1 Force Watching Dog Timer time-out event; this bit is self-clearing. Bit 1 : Enable Power LED 1Hz rate toggle pulse with 50% duty cycle , R/W = 1 Enable = 0 Disable Bit 0 : Watching Dog Timer Status, R/W = 1 Watching Dog Timer time-out occurred. = 0 Watching Dog Timer counting
*Note : 1). Internal logic provides an 1us Debounce Filter to reject the width of P20 pulse less than 1us. 2). The P20 signal that coming from Debounce Filter is ORed with the signal generated by the Force Time-out bit and then connect to set the Bit 0(Watching Dog Timer Status). The ORed signal is self-clearing.
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11. SPECIFICATIONS
11.1 Absolute Maximum Ratings
PARAMETER Power Supply Voltage Input Voltage RTC Battery Voltage VBAT Operating Temperature Storage Temperature RATING -0.5 to 7.0 -0.5 to VDD+0.5 4.0 to 1.8 0 to +70 -55 to +150 UNIT V V V C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
11.2 DC CHARACTERISTICS
(Ta = 0 C to 70 C, VDD = 5V 10%, VSS = 0V) PARAMETER RTC Battery Quiescent Current ACPI Stand-by Power Supply Quiescent Current SYM. IBAT IBAT MIN. TYP. MAX. 2.4 2.0 UNIT uA mA CONDITIONS VBAT = 2.5 V VSB = 5.0 V, All ACPI pins are not connected.
I/O8t - TTL level bi-directional pin with source-sink capability of 8 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V A A V V 0.4 2.4 +10 -10 V V A A IOL = 6 mA IOH = - 6 mA VIN = VDD VIN = 0V IOL = 8 mA IOH = - 8 mA VIN = VDD VIN = 0V
I/O6t - TTL level bi-directional pin with source-sink capability of 6 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.0 0.8
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W83977F/ W83977AF
PRELIMINARY
11.2 DC CHARACTERISTICS, continued PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS
I/O8 - CMOS level bi-directional pin with source-sink capability of 8 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 3.5 + 10 - 10 0.7xVDD 0.4 0.3xVDD V V V V A A V V 0.4 3.5 + 10 - 10 V V A A IOL = 12 mA IOH = - 12 mA VIN = VDD VIN = 0V IOL = 8 mA IOH = - 8 mA VIN = VDD VIN = 0V
I/O12 - CMOS level bi-directional pin with source-sink capability of 12 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 0.7xVDD 0.3xVDD
I/O16u - CMOS level bi-directional pin with source-sink capability of 16 mA, with internal pull-up resistor Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 3.5 + 10 - 10 0.7xVDD 0.4 0.3xVDD V V V V A A IOL = 16 mA IOH = - 16 mA VIN = VDD VIN = 0V
I/OD16u - CMOS level Open-Drain pin with source-sink capability of 16 mA, with internal pull-up resistor Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 3.5 + 10 - 10 0.7xVDD 0.4 0.3xVDD V V V V A A IOL = 16 mA IOH = - 16 mA VIN = VDD VIN = 0V
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W83977F/ W83977AF
PRELIMINARY
11.2 DC CHARACTERISTICS, continued PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS
I/O12t - TTL level bi-directional pin with source-sink capability of 12 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 + 10 - 10 2.0 0.4 0.8 V V V V A A V V 0.4 2.4 + 10 - 10 V V A A V V IOL = 24 mA IOH = - 24 mA VIN = VDD VIN = 0V IOL = 12 mA IOH = - 12 mA VIN = VDD VIN = 0V
I/O24t - TTL level bi-directional pin with source-sink capability of 24 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.0 0.8
OUT8t - TTL level output pin with source-sink capability of 8 mA Output Low Voltage Output High Voltage VOL VOH 2.4 0.4 IOL = 8 mA IOH = - 8 mA
OUT12t - TTL level output pin with source-sink capability of 12 mA Output Low Voltage Output High Voltage VOL VOH 2.4 0.4 V V IOL = 12 mA IOH = -12 mA
OD12 - Open-drain output pin with sink capability of 12 mA Output Low Voltage VOL 0.4 V IOL = 12 mA OD24 - Open-drain output pin with sink capability of 24 mA Output Low Voltage VOL 0.4 V IOL = 24 mA INt - TTL level input pin Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage VIL VIH ILIH ILIL 2.0 +10 -10 0.8 V V A A VIN = VDD VIN = 0 V
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PRELIMINARY
11.2 DC CHARACTERISTICS, continued PARAMETER INc - CMOS level input pin Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage VIL VIH ILIH ILIL 0.7xVDD +10 -10 0.3xVDD V V A A V V V +10 -10 A A V V +10 -10 A A V V V +10 -10 A A V V V +10 -10 A A VIN = VDD VIN = 0 V VIN = VDD VIN = 0 V SYM. MIN. TYP. MAX. UNIT CONDITIONS
INcs - CMOS level Schmitt-triggered input pin Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage VtVt+ VTH ILIH ILIL 1.3 3.2 1.5 1.5 3.5 2 1.7 3.8 VDD = 5 V VDD = 5 V VDD = 5 V VIN = VDD VIN = 0 V
INcu - CMOS level input pin with internal pull-up resistor Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage VIL VIH ILIH ILIL 0.7xVDD 0.7xVDD
INts - TTL level Schmitt-triggered input pin Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage VtVt+ VTH ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 1.1 2.4 VDD = 5 V VDD = 5 V VDD = 5 V VIN = VDD VIN = 0 V
INtsu - TTL level Schmitt-triggered input pin with internal pull-up resistor Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage VtVt+ VTH ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 1.1 2.4 VDD = 5 V VDD = 5 V VDD = 5 V VIN = VDD VIN = 0 V
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W83977F/ W83977AF
PRELIMINARY
11.3 AC Characteristics
11.3.1 FDC: Data rate = 1 MB, 500 KB, 300 KB, 250 KB/sec. PARAMETER SA9-SA0, AEN, DACK , CS, setup time to IOR o SA9-SA0, AEN, DACK , hold time for IOR o IOR width Data access time from IOR o Data hold from IOR o SD to from IOR o IRQ delay from IOR o SA9-SA0, AEN, DACK , setup time to IOW o SA9-SA0, AEN, DACK , hold time for IOW o IOW width Data setup time to IOW o Data hold time from IOW o IRQ delay from IOW o DRQ cycle time DRQ delay time DACK o DRQ to DACK delay DACK width IOR delay from DRQ IOW delay from DRQ SYM. TAR TAR TRR TFD TDH TDF TRI TAW TWA TWW TDW TWD TWI TMCY TAM TMA TAA TMR TMW 0 260/430 /510 0 0 27 50 25 0 60 60 0 360/570 /675 CL = 100 pf CL = 100 pf CL = 100 pf 10 10 50 360/570 /675 TEST CONDITIONS MIN. 25 0 80 80 TYP.
(NOTE 1)
MAX.
UNIT nS nS nS nS nS nS nS nS nS nS nS nS nS S nS nS nS nS nS
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W83977F/ W83977AF
PRELIMINARY
11.3.1 AC Characteristics, FDC continued PARAMETER IOW or IOR response time from DRQ TC width RESET width INDEX width DIR setup time to STEP DIR hold time from STEP STEP pulse width STEP cycle width WD pulse width Write precompensation
Notes: 1. Typical values for T = 25 C and normal supply voltage. 2. Programmable from 2 mS through 32 mS in 2 mS increments.
SYM. TMRW TTC TRST TIDX TDST TSTD TSTP TSC TWDD TWPC
TEST CONDITIONS
MIN.
TYP. (NOTE 1) 6/12 /20/24
MAX.
UNIT S nS S S S S
135/220 /260 1.8/3/3. 5 0.5/0.9 /1.0 1.0/1.6 /2.0 24/40/48 6.8/11.5 /13.8 Note 2 100/185 /225 100/138 /225 7/11.7 /14 Note 2 125/210 /250 125/210 /250 7.2/11.9 /14.2 Note 2 150/235 /275 150/235 /275
S S S S
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W83977F/ W83977AF
PRELIMINARY
11.3.2 UART/Parallel Port PARAMETER Delay from Stop to Set Interrupt Delay from IOR Reset Interrupt Delay from Initial IRQ Reset to Transmit Start Delay from IOW to Reset interrupt Delay from Initial IOW to interrupt Delay from Stop to Set Interrupt Delay from IOR to Reset Interrupt Delay from IOR to Output Set Interrupt Delay from Modem Input Reset Interrupt Delay from IOR Interrupt Active Delay Interrupt Inactive Delay Baud Divisor SYMBOL TSINT TRINT TIRS THR TSI TSTI TIR TMWO TSIM TRIM TIAD TIID
N
TEST CONDITIONS
MIN. 9/16
MAX.
UNIT Baud Rate
100 pf Loading 1/16 100 pf Loading 9/16
1 8/16 175 16/16 1/2
S Baud Rate nS Baud Rate Baud Rate nS nS nS nS nS nS
100 pF Loading 100 pF Loading
250 200 250 250
100 pF Loading 100 pF Loading 100 pF Loading
25 30 2 -1
16
11.3.3 Parallel Port Mode Parameters PARAMETER PD0-7, INDEX , STROBE, AUTOFD Delay from IOW IRQ Delay from ACK , nFAULT IRQ Delay from IOW IRQ Active Low in ECP and EPP Modes ERROR Active to IRQ Active SYM. t1 t2 t3 t4 t5 200 MIN. TYP. MAX. 100 60 105 300 105 UNIT nS nS nS nS nS
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PRELIMINARY
11.3.4 EPP Data or Address Read Cycle Timing Parameters PARAMETER Ax Valid to IOR Asserted IOCHRDY Deasserted to IOR Deasserted IOR Deasserted to Ax Valid IOR Deasserted to IOW or IOR Asserted IOR Asserted to IOCHRDY Asserted PD Valid to SD Valid IOR Deasserted to SD Hi-Z (Hold Time) SD Valid to IOCHRDY Deasserted WAIT Deasserted to IOCHRDY Deasserted PD Hi-Z to PDBIR Set WRITE Deasserted to IOR Asserted WAIT Asserted to WRITE Deasserted Deasserted to WRITE Modified IOR Asserted to PD Hi-Z WAIT Asserted to PD Hi-Z Command Asserted to PD Valid Command Deasserted to PD Hi-Z WAIT Deasserted to PD Drive WRITE Deasserted to Command PBDIR Set to Command PD Hi-Z to Command Asserted Asserted to Command Asserted WAIT Deasserted to Command Deasserted Time out PD Valid to WAIT Deasserted PD Hi-Z to WAIT Deasserted SYM. t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 MIN. 40 0 10 40 0 0 0 0 60 0 0 0 60 0 60 0 0 60 1 0 0 0 60 10 0 0 20 30 195 180 12 190 185 190 50 180 24 75 40 85 160 nS nS S nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS S 10 MAX. UNIT nS nS nS
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PRELIMINARY
11.3.5 EPP Data or Address Write Cycle Timing Parameters PARAMETER Ax Valid to IOW Asserted SD Valid to Asserted IOW Deasserted to Ax Invalid WAIT Deasserted to IOCHRDY Deasserted Command Asserted to WAIT Deasserted IOW Deasserted to IOW or IOR Asserted IOCHRDY Deasserted to IOW Deasserted WAIT Asserted to Command Asserted IOW Asserted to WAIT Asserted PBDIR Low to WRITE Asserted WAIT Asserted to WRITE Asserted WAIT Asserted to WRITE Change IOW Asserted to PD Valid WAIT Asserted to PD Invalid PD Invalid to Command Asserted IOW to Command Asserted WAIT Asserted to Command Asserted WAIT Deasserted to Command Deasserted Command Asserted to WAIT Deasserted Time out Command Deasserted to WAIT Asserted IOW Deasserted to WRITE Deasserted and PD invalid SYM. t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 MIN. 40 10 10 0 10 40 0 60 0 0 60 60 0 0 10 5 60 60 0 10 0 0 35 210 190 10 12 185 185 50 24 160 70 MAX. UNIT nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS S S nS nS
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PRELIMINARY
11.3.6 Parallel Port FIFO Timing Parameters PARAMETER DATA Valid to nSTROBE Active nSTROBE Active Pulse Width DATA Hold from nSTROBE Inactive BUSY Inactive to PD Inactive BUSY Inactive to nSTROBE Active nSTROBE Active to BUSY Active SYMBOL t1 t2 t3 t4 t5 t6 MIN. 600 600 450 80 680 500 MAX. UNIT nS nS nS nS nS nS
11.3.7 ECP Parallel Port Forward Timing Parameters PARAMETER nAUTOFD Valid to nSTROBE Asserted PD Valid to nSTROBE Asserted BUSY Deasserted to nAUTOFD Changed BUSY Deasserted to PD Changed nSTROBE Deasserted to BUSY Deasserted BUSY Deasserted to nSTROBE Asserted nSTROBE Asserted to BUSY Asserted BUSY Asserted to nSTROBE Deasserted SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 MIN. 0 0 80 80 0 80 0 80 180 200 MAX. 60 60 180 180 UNIT nS nS nS nS nS nS nS nS
11.3.8 ECP Parallel Port Reverse Timing Parameters PARAMETER PD Valid to nACK Asserted nAUTOFD Deasserted to PD Changed nAUTOFD Asserted to nACK Asserted nAUTOFD Deasserted to nACK Deasserted nACK Deasserted to nAUTOFD Asserted PD Changed to nAUTOFD Deasserted SYMBOL t1 t2 t3 t4 t5 t6 MIN. 0 0 0 0 80 80 200 200 MAX. UNIT nS nS nS nS nS nS
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PRELIMINARY
11.3.9 KBC Timing Parameters NO. T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 DESCRIPTION Address Setup Time from WRB Address Setup Time from RDB WRB Strobe Width RDB Strobe Width Address Hold Time from WRB Address Hold Time from RDB Data Setup Time Data Hold Time Gate Delay Time from WRB RDB to Drive Data Delay RDB to Floating Data Delay Data Valid After Clock Falling (SEND) K/B Clock Period K/B Clock Pulse Width Data Valid Before Clock Falling (RECEIVE) K/B ACK After Finish Receiving RC Fast Reset Pulse Delay (8 Mhz) RC Pulse Width (8 Mhz) Transmit Timeout Data Valid Hold Time Input Clock Period (6-12 Mhz) Duration of CLK inactive Duration of CLK active Time from inactive CLK transition, used to time when the auxiliary device sample DATA Time of inhibit mode Time from rising edge of CLK to DATA transition Duration of CLK inactive Duration of CLK active Time from DATA transition to falling edge of CLK 0 83 30 30 5 100 5 30 30 5 167 50 50 25 300 T28-5 50 50 25 20 10 4 20 2 6 2 3 0 MIN. 0 0 20 20 0 0 50 0 10 30 40 20 4 MAX. UNIT nS nS nS nS nS nS nS nS nS nS nS S S S S S S S mS S nS S S S S S S S S
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W83977F/ W83977AF
PRELIMINARY
11.3.10 SYMBOL tWGO tSWP tSWE GPIO, ACPI, ROM Interface Timing Parameters PARAMETER Write data to GPIO update SWITCH pulse width Delay from SWITCH events to PSCTRL , and from SWITCH Off event to SMI tPORW tPOWR tRIO SMI pulse width (edge mode) Delay from APCI Reg.1 write to SMI inactive (level mode) Delay from RIA, B KCLK, MCLK, PWAKIN1, PWAKIN2 to PSCTRL tRPO tRTO tRINW Delay from PHRI pulse to PSCTRL Delay from PHRI pulse train to PSCTRL PHRI width (high and low time) 0.125 10 25 0.190 sec sec ns 30 90 25 s nsec 16 14 16 MIN. MAX. 300(Note 1) UNIT ns msec msec
-
25
nsec
Note : Refer to Microprocessor Interface Timing for Read Timing.
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W83977F/ W83977AF
PRELIMINARY
12. TIMING WAVEFORMS
12.1 FDC
Write Date
WD TWDD
Processor Read Operation
SA0-SA9 AEN CS DACK TRR IOR TFD TDF D0-D7 INDEX TR IRQ TIDX TDH TAR TRA
Index
TIDX
Processor Write Operation
SA0-SA9 AEN DACK IOW TWD TAW TWW TWA TC
Terminal Count
TTC
Reset
TDW
D0-D7
RESET
TWI IRQ TRST
DMA Operation
Drive Seek operation
TAM DRQ DIR TMCY DACK TMA IOW or IOR TMW (IOW) TMR (IOR) TSC TAA TDST TMRW STEP TSTP TSTD
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W83977F/ W83977AF
PRELIMINARY
12.2 UART/Parallel
Receiver Timing
SIN (RECEIVER INPUT DATA) STAR DATA BITS (5-8) PARITY STOP TSINT TRINT
IRQ3 or IRQ4 IOR (READ RECEIVER BUFFER REGISTER)
Transmitter Timing
SERIAL OUT (SOUT) THRS IRQ3 or IRQ4 THR IOW (WRITE THR) THR TSI TIR IOR (READ TIR) STAR DATA (5-8) PARITY STOP (1-2) STAR TSTI
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W83977F/ W83977AF
PRELIMINARY
12.2.1 Modem Control Timing MODEM Control Timing
IOW (WRITE MCR)
RTS,DTR
/
x x x x x
x x x x
x x x x
o TMWO
x x x
/
x x x x
x x x x
oTMWO
CTS,DSR DCD IRQ3 or IRQ4 IOR (READ MSR)
/ o TSIM
x x x x x
/ / oTRIM x
x x x
x x x
o TSIM
/ o o /
RI
Printer Interrupt Timing
x x x x x x
ACK
/
IRQ7
x x x x x
o TLAD
/
x x x xx TRIM x x TSIM x x x x x x x x x x x x x x x TLID x x x x
x x x x x x x
o
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W83977F/ W83977AF
PRELIMINARY
12.3 Parallel Port
12.3.1 Parallel Port Timing
IOW t1 INIT, STROBE AUTOFD, SLCTIN PD<0:7> ACK t2 IRQ (SPP) IRQ (EPP or ECP) nFAULT (ECP) ERROR (ECP) t5 t2 IRQ t4 t3 t4
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W83977F/ W83977AF
PRELIMINARY
12.3.2 EPP Data or Address Read Cycle (EPP Version 1.9)
t3 A<0:10> IOR t1 t6 SD<0:7> t8 t5 IOCHRDY t10 t9 t2 t7 t4
t13 t14 WRITE t16 t17 PD<0:7> t21 t22 t23 t24 t25
t15
t18
t19
t20
ADDRSTB DATASTB
t26
t27
t28
WAIT
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W83977F/ W83977AF
PRELIMINARY
12.3.3 EPP Data or Address Write Cycle (EPP Version 1.9)
t3 t4 A10-A0 SD<0:7> t1 IOW IOCHRDY t9 t10 t11 t13 t15 t16 t17 DATAST ADDRSTB t19 t20 WAIT t22 PBDIR t21 t2 t7 t8 t5 t6
t12 t14
WRITE PD<0:7>
t18
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W83977F/ W83977AF
PRELIMINARY
12.3.4 EPP Data or Address Read Cycle (EPP Version 1.7)
t3 A<0:10> IOR t1 t6 t7 SD<0:7> t8 t5 IOCHRDY t10 t9 t2 t4
t13 t14 WRITE t16 t17 PD<0:7> t21 t22 t23 t25 t24
t15
t18
t19
t20
ADDRSTB DATASTB
t26
t27
t28
WAIT
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W83977F/ W83977AF
PRELIMINARY
12.3.5 EPP Data or Address Write Cycle (EPP Version 1.7)
t3 t4 A10-A0 SD<0:7> t1 IOW IOCHRDY t9 t10 t11 t13 t15 t16 t17 DATAST ADDRSTB t19 t20 WAIT t2 t7 t8 t5 t6
t22 t22
WRITE PD<0:7>
t18
12.3.6
Parallel Port FIFO Timing
t4 t3 PD<0:7> t1 >| t2 > t5 >| >| >|
nSTROBE
t6 BUSY
>|
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W83977F/ W83977AF
PRELIMINARY
12.3.7 ECP Parallel Port Forward Timing
t3 nAUTOFD t4 PD<0:7> t1 t2 t6 nSTROBE t5 BUSY t7 t5 t8
12.3.8
ECP Parallel Port Reverse Timing
t2 PD<0:7> t1 t3 nACK t5 nAUTOFD t6 t5
t4
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W83977F/ W83977AF
PRELIMINARY
12.4 KBC
12.4.1 Write Cycle Timing
A2, CSB
T1 T3 ACTIVE T7 T8 T5
WRB
D0~D7 GA20 OUTPUT PORT FAST RESET PULSE RC FE COMMAND
DATA IN T9
T17
T18
12.4.2
Read Cycle Timing
A2,CSB AEN
T2 T4 T6
RDB
ACTIVE T10 T11
D0-D7
DATA OUT
12.4.3
Send Data to K/B
CLOCK (KCLK)
T12 T14 D0 D1 D2 D3 T13 D4 T19 D5 D6 D7 P T16
SERIAL DATA (KDAT)
START
STOP
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W83977F/ W83977AF
PRELIMINARY
12.4.4 Receive Data from K/B
CLOCK (KCLK)
T15 T14 D0 D1 D2 D3 D4 T13 D5 D6 D7 P
SERIAL DATA (T1)
START T20
STOP
12.4.5
Input Clock
CLOCK CLOCK T21
12.4.6
Send Data to Mouse
MCLK
T25 T22 T23 T24
MDAT
START Bit
D0
D1
D2
D3
D4
D5
D6
D7
P
STOP Bit
12.4.7
Receive Data from Mouse
MCLK
T29 T26 T27 T28
MDAT
START
D0
D1
D2
D3
D4
D5
D6
D7
P
STOP Bit
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W83977F/ W83977AF
PRELIMINARY
12.5 GPIO Write Timing Diagram
A0-A15 IOW D0-7 GPIO10-17 GPIO20-25
PREVIOUS STATE
VALID
VALID
VALID tWGO
12.6 Master Reset (MR) Timing
Vcc
tVMR
MR
12.7 ACPI
12.7.1 PANSW Trigger and PSCTRL Timing
VOH V OL HI-Z V OL HI-Z/VOH V OL VOH V OL
edge: tPORW tSWP tSWP
PANSW
tSWE
tSWE
PSCTRL
SMI
WR
Level: tPRL
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W83977F/ W83977AF
PRELIMINARY
12.7.2 RIA , RIB , KLCK, MCLK, PWAKIN1, PWAKIN2 Trigger and PSCTRL Timing
RIA, RIB KCLK, MCLK PWAKIN1, PWAKIN2
V OH V OL HI-Z V OL
tRIO
PSCTRL
12.7.3
PHRI Trigger and PSCTRL Timing
PHRI V OH V OL
tRINW tRINW tRPO
PSCTRL
HI-Z V OL
tRTO
13. APPLICATION CIRCUITS
13.1 Parallel Port Extension FDD
JP13
WE2/SLCT WD2/PE MOB2/BUSY DSB2/ACK PD7 PD6 PD5 DCH2/PD4 RDD2/PD3 STEP2/SLIN WP2/PD2 DIR2/INIT TRK02/PD1 HEAD2/ERR IDX2/PD0 RWC2/AFD STB 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1
JP 13A
DCH2 HEAD2 RDD2
WP2
TRK02 WE2 WD2 STEP2 DIR2 MOB2 DSB2 IDX2
RWC2
34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
EXT FDC
PRINTER PORT
Parallel Port Extension FDD Mode Connection Diagram
Publication Release Date: March 1998 Revision 0.58
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PRELIMINARY
13.2 Parallel Port Extension 2FDD
JP13
WE2/SLCT WD2/PE MOB2/BUSY DSB2/ACK DSA2/PD7 MOA2/PD6 PD5 DCH2/PD4 RDD2/PD3 STEP2/SLIN WP2/PD2 DIR2/INIT TRK02/PD1 HEAD2/ERR IDX2/PD0 RWC2/AFD STB 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1
JP 13A
DCH2 HEAD2 RDD2
WP2
TRK02 WE2 WD2 STEP2 DIR2 MOB2 DSA2 DSB2 MOA2 IDX2
RWC2
34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
EXT FDC
PRINTER PORT
Parallel Port Extension 2FDD Connection Diagram
13.3 Four FDD Mode
74LS139 W83977F DSA DSB MOA MOB G2 A2 B2 G1 A1 B1 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 DSA DSB DSC DSD MOA MOB MOC MOD 7407(2)
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W83977F/ W83977AF
PRELIMINARY
14. ORDERING INFORMATION
PART NO. W83977F-P W83977F-A W83977AF-P W83977AF-A KBC FIRMWARE Phoenix MultiKey/42 AMIKEY-2 AMIKEY-2
TM TM TM
REMARKS without FIR, 3rd UART without FIR, 3rd UART with FIR, 3rd UART with FIR, 3rd UART
Phoenix MultiKey/42
TM
15. HOW TO READ THE TOP MARKING
Example: The top marking of W83977F-A
inbond
W83977TF-A
(c) AM. MEGA. 87-96 719AB27039520
1st line: Winbond logo 2nd line: the type number: W83977F-A 3rd line: the source of KBC F/W -- American Megatrends IncorporatedTM 4th line: Tracking code 709 A B 2 6519520 709: packages made in '97, week 09 A: assembly house ID; A means ASE, S means SPIL B: IC revision; B means version B, C means version C 2: wafers manufactured in Winbond FAB 2 6519520: wafer production series lot number
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Publication Release Date: March 1998 Revision 0.58
W83977F/ W83977AF
PRELIMINARY
16. PACKAGE DIMENSIONS
(128-pin QFP)
HE E
102 65
Symbol
Dimension in mm
Dimension in inch
Min
0.25 2.57 0.10 0.10 13.90 19.90
Nom
0.35 2.72 0.20 0.15 14.00 20.00 0.50
Max
0.45 2.87 0.30 0.20 14.10 20.10
Min
0.010 0.101 0.004 0.004 0.547 0.783
Nom Max
0.014 0.107 0.008 0.006 0.551 0.787 0.020 0.018 0.113 0.012 0.008 0.555 0.791
103
64
D
HD
128
39
1
e
b
38
A1 A2 b c D E e HD HE L L1 y 0
c
17.00 23.00 0.65
17.20 23.20 0.80 1.60
17.40 23.40 0.95
0.669 0.905 0.025
0.677 0.913 0.031 0.063
0.685 0.921 0.037
0.08 0 7 0
0.003 7
A A2 See Detail F Seating Plane A1 L L1 Detail F
Note:
1.Dimension D & E do not include interlead flash. 2.Dimension b does not include dambar protrusion/intrusion . 3.Controlling dimension : Millimeter 4.General appearance spec. should be based on final visual inspection spec.
y
5. PCB layout please use the "mm".
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: March 1998 Revision 0.58

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